Clock gating is supported by commercial tools as a power optimization feature based on the guard signal described in HDL (structural method). However, the identification of control signals for gated registers is hard and designer-intensive work. Besides, since the clock gating cells also consume power, it is imperative to minimize the number of inserted clock gating cells and their switching activities for power optimization. In this paper, we propose an automatic multi-stage clock gating algorithm with ILP (Integer Linear Programming) formulation, including clock gating control candidate extraction, constraints construction and optimum control signal selection. By multi-stage clock gating, unnecessary clock pulses to clock gating cells can be avoided by other clock gating cells, so that the switching activity of clock gating cells can be reduced. We find that any multi-stage control signals are also single-stage control signals, and any combination of signals can be selected from single-stage candidates. The proposed method can be applied to 3 or more cascaded stages. The multi-stage clock gating optimization problem is formulated as constraints in LP format for the selection of cascaded clock-gating order of multi-stage candidate combinations, and a commercial ILP solver (IBM CPLEX) is applied to obtain the control signals for each register with minimum switching activity. Those signals are used to generate a gate level description with guarded registers from original design, and a commercial synthesis and layout tools are applied to obtain the circuit with multi-stage clock gating. For a set of benchmark circuits and a Low Density Parity Check (LDPC) Decoder (6.6k gates, 212 F.F.s), the proposed method is applied and actual power consumption is estimated using Synopsys NanoSim after layout. On average, 31% actual power reduction has been obtained compared with original designs with structural clock gating, and more than 10% improvement has been achieved for some circuits compared with single-stage optimization method. CPU time for optimum multi-stage control selection is several seconds for up to 25k variables in LP format. By applying the proposed clock gating, area can also be reduced since the multiplexors controlling register inputs are eliminated.

Software Radio has been proposed in the 1990s as the solution to flexible transceiver design for future wireless systems. Potential advantages and drawbacks of this approach have been described and analysed in verbose format in many articles. However, a mathematical perspective of the software radio design problem is to be found in the literature only once. Despite this attempt to develop a sound formal description the conclusions do not reach beyond algorithm design. Open issues in system design are often mentioned, but remain unresolved hitherto. We develop a novel mathematical perspective of software radio, and we formulate the design problem accordingly, by means of an integer linear programming (ILP) representation. This type of problem is well-known in computer science and operations research, but it has never been linked to software radio design before. In a first approach to solve the ILP problem we reduce it to a scheduling problem with processor constraints. In the remainder of the theoretical section we introduce the notions of granularity G and speedup s to assess the quality of modular implementations. A random runtime argument leads the way to a system-theoretic approach to modular design issues such as maximizing speedup over a great number of different implementations. For the special case G = 1 we deduce the speedup potential of a primitive graph in analytical form. In the experimental section we compare simulation results to our theory, and we extend the experiments to a more complicated graph which stems from a real software radio design project. The paper concludes with a discussion and a brief outlook to future research issues.