The influence of noise is an important problem on image acquisition and transmission stages. The traditional image denoising approaches only analyzing the pixels of local region with a moving window, which calculated by neighbor pixels to denoise. Recently, this research has been focused on the transform domain and feature space. Compare with the traditional approaches, the global multi-scale analyzing and unchangeable noise distribution is the advantage. Apparently, the estimation based methods can be used in transform domain and get better effect. This paper proposed a new approach to image denoising in orthonormal wavelet domain. In this paper, we adopt Stein's unbiased risk estimate (SURE) based method to denoise the low-frequency bands and the feature patches distance constraint (FPDC) method also be proposed to estimate the noise free bands in Wavelet domain. The key point is that how to divide the lower frequency sub-bands and the higher frequency sub-bands, and do interscale SURE and intrascale FPDC, respectively. We compared our denoising method with some well-known and new denoising algorithms, the experimental results show that the proposed method can give better performance and keep more detail information in most objective and subjective criteria than other methods.

The progress made in large-scale integration of the baseband circuits of digital cellular phones now makes it possible to implement a voice CODEC and its related functions in the baseband LSI rather than through a general-purpose digital signal processor. This paper describes an improved hardware solution that enables efficient application of the PSI-CELP CODEC-- the most complex CODEC for mobile systems--to the PDC half-rate system through its implementation as a DSP macro in a low-voltage, large-scale LSI. Specific circuit blocks are added as hardware engines to a general-purpose DSP-oriented core. These specific engines were implemented as peripheral circuits for a DSP macro that can be used as a single DSP with an added I/O circuit and is suitable for use in future highly integrated mobile baseband chips. With the assistance of these hardware engines and some additional ALU instructions to achieve efficient programming, the machine speed required for the CODEC can be relatively slow, thus allowing the same architecture to be repeatedly used without needing to set the transistor threshold voltage too low even when the use of deeper sub-micron technologies require a chip to run at a lower supply voltage. We evaluated this DSP-macro architecture using a 0.35 µm CMOS technology test chip. Then we developed a commercial base version using 0.25 µm technology and verified that it can operate at 1.2 V and that the PSI-CELP CODEC can be done at 40 MIPS with power consumption of 11 mW. We also verified that the circuit design can be applied up to 0.18 µm technology with a single threshold voltage of 0.3 V. Thus, the design of the DSP macro incorporating the hardware engines provides a great deal of flexibility that should allow its use in chips based on future technologies and the voice CODEC firmware can be effectively re-used. Although the DSP macro architecture was designed mainly through PSI-CELP application analysis, it can process other voice CODECs such as the AMR CODEC for third-generation mobile applications as well as some other mobile baseband functions such as channel CODECs. This approach can also be refined to permit its application to, for example, high-quality audio CODECs.

Internet access via mobile communications networks is growing rapidly; NTT DoCoMo's Internet access service using cellular phones, known as i-mode and started in February 1999, is no exception. The i-mode service enables the user to send e-mail and access Web sites for a variety of information through simple operation of a mobile terminal equipped with a browser. As a result, the traffic to be carried by the PDC (Personal Digital Cellular)-- Packet mobile communication network, which is used to provide the i-mode service, is also increasing rapidly. To meet this growing demand, the switching systems in place are being either increased in capacity or replaced by more powerful ones. To plan this effectively, it is necessary to make an accurate evaluation of the i-mode processing capacity. We have developed a new method of evaluating processing capacity, which is based on the conventional method but takes account of the characteristics specific to the PDC-Packet network. This paper discusses the method of evaluating the processing capacity of switching systems used in the PDC-Packet mobile network.

By using the gain expansive and compressive characteristics of two FET to compensate for the phase shift at large signal, one can greatly improve Adjacent Channel Power Ratio (ACPR) of the power amplifier. This 3 to 5 dB improvement result was verified experimentally by selecting the biasing point and the gain level of the first and second stage amplifiers. This MCM circuit-level technique is more attractive to achieve low cost and good ACPR design. As examples, some novel high efficiency power amplifiers with good ACPR for the handset applications are developed by this method. Those mass producible 0.12 cc volume (7.87.82.0 mm) multi-chip module power amplifiers (MCM PA) employ state-of-the-art enhancement GaAs HJFET devices that need only a single power supply.

This paper describes the results of a series of laboratory experiments for performance evaluations of our proposed Maximum Likelihood Sequence Estimation (MLSE) based interference canceller, the Interference Canceling Equalizer (ICE), which can cancel both co-channel interference (CCI) and inter-symbol interference (ISI). To verify the feasibility of ICE for the Japanese cellular communications system, a standard of which has been released under the name of Personal Digital Cellular (PDC) system, a prototype system was constructed using 27 TI TMS320C40 Digital Signal Processor (DSP) chips. The ICE prototype works in real-time on the PDC air interface, major specifications of which are π/4 QDPSK 21 k symbols/s 3-channel time-division multiple-access (TDMA). Two-branch diversity reception is used to enhance the signal detection performance of ICE. In the experiments, BER performances were evaluated using the prototype system. Under a single-path Rayleigh fading and a single CCI condition, the ICE receiver attains the BER of less than 310-2 with the negative values of the average CIR: for fD = 5 Hz and 40 Hz, the average CIR more than -20 dB and -10 dB, respectively. Under a double-path Rayleigh fading and a single CCI condition, the ICE receiver attains the BER of less than 1.510-2 with the negative values of the average CIR: for fD = 5 Hz and 40 Hz, the average CIR more than -20 dB and -10 dB, respectively. The laboratory test results suggest that the ICE receiver has potential for system capacity enhancement.

In this paper, we propose fast block matching criteria to reduce the implementation complexity of motion estimation in VLSI video coders. Based on generalized quantization of pixel difference measures, the block matching criteria combined with bitmap exclusive-OR (XOR) concept can be realized by short length adders and a multi-input binary counter. The proposed approach can be treated as a generalization of the pixel difference classification (PDC) criterion. Simulation results show that the proposed block-matching criteria along with various block search algorithms achieve better results than the PDC and obtain nearly the same performance as the mean absolute difference (MAD) criterion. However, the complete gate-level synthesis of the proposed matching criterion is much less than those of the MAD and the PDC in the VLSI implementation.

A new high performance digital signal processor (DSP) that lowers power consumption, reduces chip count, and enables system cost savings for wireless communications applications was developed. The new device contains high performance, hard-wired functionality with a specialized instruction set to effectively implement the worldwide digital cellular standard algorithms, including GSM, PDC and NADC, and also features both full rate and future half rate processing by software modules. The device provides a wider operating voltage ranging from 1.5 V to 5.5 V using 5 V process based on the market requirement of 5 V supply voltage, even though a power supply voltage in most applications will be shifted to 3 V. Several circuits was newly developed to achieve low power consumption and high speed operation at both 5 V and 3 V process using the same data base. The device also features over 50 MIPS of processing power with low power consumption and 100 nA stand-by current at either 3 V or 5 V. One remarkable advantage is a flexible CPU core approach for the future spin-off devices with different ROM/RAM configurations and peripheral modules without requiring any CPU design changes. This paper describes the architecture of a lower power and high speed design with effective hardware and software modules implementations.