A new high performance digital signal processor (DSP) that lowers power consumption, reduces chip count, and enables system cost savings for wireless communications applications was developed. The new device contains high performance, hard-wired functionality with a specialized instruction set to effectively implement the worldwide digital cellular standard algorithms, including GSM, PDC and NADC, and also features both full rate and future half rate processing by software modules. The device provides a wider operating voltage ranging from 1.5 V to 5.5 V using 5 V process based on the market requirement of 5 V supply voltage, even though a power supply voltage in most applications will be shifted to 3 V. Several circuits was newly developed to achieve low power consumption and high speed operation at both 5 V and 3 V process using the same data base. The device also features over 50 MIPS of processing power with low power consumption and 100 nA stand-by current at either 3 V or 5 V. One remarkable advantage is a flexible CPU core approach for the future spin-off devices with different ROM/RAM configurations and peripheral modules without requiring any CPU design changes. This paper describes the architecture of a lower power and high speed design with effective hardware and software modules implementations.

A 100MIPS high speed and low power fixed point Digital Signal Processor (DSP) has been developed applying 0.45µm CMOS TLM technology. The DSP contains a 16-bit32K full CMOS static RAM with a hierarchical low power architecture. The device is a RAM based DSP with a total of 4.2 million transistors and a new low power design and process which enabled an approximate 50% reduction in power as compared to conventional DSPs at 40 MHz. In order to cover very wide application requirements, this DSP is capable of operating at 1.0 V for DSP core and 3.3 V for I/O. This was achieved by new level shifter circuitry to interface with cost effective 3 V external commodity products and confirmed 80% of power reduction at Core VDD=2.0 V, I/O VDD=3.3 V at 40MHz. This paper describes the new features of the high speed and low power DSP.

High-speed and low-power DSPs have been developed for versatile applications, especially for digital communications. These DSPs contain a 16-bit fixed point DSP core with multiple buses, highly tuned instruction set and low-power architecture, featuring 0.45 mA/MIPS, 100-120 MIPS performance by a single CPU core, 200 MIPS performance by dual CPU core architecture, respectively and also contain a 1.2 V low-voltage DSP core with 30 MIPS performance for super low-power applications. In this paper, new architecture VIA2 programming ROM for high-speed and new D flip-flop circuit considering the impact of pocket implantation process for low power are discussed, including key C-MOS process technology.