A 100MIPS high speed and low power fixed point Digital Signal Processor (DSP) has been developed applying 0.45µm CMOS TLM technology. The DSP contains a 16-bit32K full CMOS static RAM with a hierarchical low power architecture. The device is a RAM based DSP with a total of 4.2 million transistors and a new low power design and process which enabled an approximate 50% reduction in power as compared to conventional DSPs at 40 MHz. In order to cover very wide application requirements, this DSP is capable of operating at 1.0 V for DSP core and 3.3 V for I/O. This was achieved by new level shifter circuitry to interface with cost effective 3 V external commodity products and confirmed 80% of power reduction at Core VDD=2.0 V, I/O VDD=3.3 V at 40MHz. This paper describes the new features of the high speed and low power DSP.

A novel SRAM cell architecture for sub-1-V high-speed operation is proposed operation is proposed that uses neither low-Vth MOSFET's nor modified cell layout patterns. A source-line, connected to the source terminals of the driver MOSFET's is controlled so that it is negative and floating in the read and write cycles, respectively. This improved the bit-line access time by 1/4-1/2 at supply voltages of 0.5-1.0 V. Limiting the bit-line swing reduces by 1/10 the writing power needed to charge them and allows faster write-recovery, as well. The achievability of low-power 100-MHz operation over a wide range of supply voltages is demonstrated.

A power-aware interconnect circuit design--called µI/O architecture--has been developed to provide low-cost system solutions for System-on-Chip (SoC) and System-in-Package (SiP) technologies. The µI/O architecture provides a common interface throughout the module enabling hierarchical I/O design for SoC and SiP. The hierarchical I/O design allows the driver size to be optimized without increasing design complexity. Moreover, it includes a signal-level converter for integrating wide-voltage-range circuit blocks and a signal wall function for turning off each block independently--without invalid signal transmission--by using an internal power switch.