µI/O Architecture: A Power-Aware Interconnect Circuit Design for SoC and SiP
Summary :
A power-aware interconnect circuit design--called µI/O architecture--has been developed to provide low-cost system solutions for System-on-Chip (SoC) and System-in-Package (SiP) technologies. The µI/O architecture provides a common interface throughout the module enabling hierarchical I/O design for SoC and SiP. The hierarchical I/O design allows the driver size to be optimized without increasing design complexity. Moreover, it includes a signal-level converter for integrating wide-voltage-range circuit blocks and a signal wall function for turning off each block independently--without invalid signal transmission--by using an internal power switch.
- Publication
- IEICE TRANSACTIONS on Electronics Vol.E87-C No.4 pp.589-597
- Publication Date
- 2004/04/01
- Publicized
- Online ISSN
- DOI
- Type of Manuscript
- Special Section PAPER (Special Section on Low-Power System LSI, IP and Related Technologies)
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Yusuke KANNO, Hiroyuki MIZUNO, Nobuhiro OODAIRA, Yoshihiko YASU, Kazumasa YANAGISAWA, "µI/O Architecture: A Power-Aware Interconnect Circuit Design for SoC and SiP" in IEICE TRANSACTIONS on Electronics,
vol. E87-C, no. 4, pp. 589-597, April 2004, doi: .
Abstract: A power-aware interconnect circuit design--called µI/O architecture--has been developed to provide low-cost system solutions for System-on-Chip (SoC) and System-in-Package (SiP) technologies. The µI/O architecture provides a common interface throughout the module enabling hierarchical I/O design for SoC and SiP. The hierarchical I/O design allows the driver size to be optimized without increasing design complexity. Moreover, it includes a signal-level converter for integrating wide-voltage-range circuit blocks and a signal wall function for turning off each block independently--without invalid signal transmission--by using an internal power switch.
URL: https://global.ieice.org/en_transactions/electronics/10.1587/e87-c_4_589/_p
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@ARTICLE{e87-c_4_589,
author={Yusuke KANNO, Hiroyuki MIZUNO, Nobuhiro OODAIRA, Yoshihiko YASU, Kazumasa YANAGISAWA, },
journal={IEICE TRANSACTIONS on Electronics},
title={µI/O Architecture: A Power-Aware Interconnect Circuit Design for SoC and SiP},
year={2004},
volume={E87-C},
number={4},
pages={589-597},
abstract={A power-aware interconnect circuit design--called µI/O architecture--has been developed to provide low-cost system solutions for System-on-Chip (SoC) and System-in-Package (SiP) technologies. The µI/O architecture provides a common interface throughout the module enabling hierarchical I/O design for SoC and SiP. The hierarchical I/O design allows the driver size to be optimized without increasing design complexity. Moreover, it includes a signal-level converter for integrating wide-voltage-range circuit blocks and a signal wall function for turning off each block independently--without invalid signal transmission--by using an internal power switch.},
keywords={},
doi={},
ISSN={},
month={April},}
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TY - JOUR
TI - µI/O Architecture: A Power-Aware Interconnect Circuit Design for SoC and SiP
T2 - IEICE TRANSACTIONS on Electronics
SP - 589
EP - 597
AU - Yusuke KANNO
AU - Hiroyuki MIZUNO
AU - Nobuhiro OODAIRA
AU - Yoshihiko YASU
AU - Kazumasa YANAGISAWA
PY - 2004
DO -
JO - IEICE TRANSACTIONS on Electronics
SN -
VL - E87-C
IS - 4
JA - IEICE TRANSACTIONS on Electronics
Y1 - April 2004
AB - A power-aware interconnect circuit design--called µI/O architecture--has been developed to provide low-cost system solutions for System-on-Chip (SoC) and System-in-Package (SiP) technologies. The µI/O architecture provides a common interface throughout the module enabling hierarchical I/O design for SoC and SiP. The hierarchical I/O design allows the driver size to be optimized without increasing design complexity. Moreover, it includes a signal-level converter for integrating wide-voltage-range circuit blocks and a signal wall function for turning off each block independently--without invalid signal transmission--by using an internal power switch.
ER -
English
