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[Keyword] VLSIC(2hit)

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  • Fully Digital Burst Modem for Satellite Multimedia Communication Systems

    Kiyoshi KOBAYASHI  Tetsu SAKATA  Yoichi MATSUMOTO  Shuji KUBOTA  

     
    PAPER-Modem and Coding

      Vol:
    E80-B No:1
      Page(s):
    8-15

    This paper presents fully digital high speed (17.6Mb/s) burst modem for Offset Quadrature Phase Shift Keying (OQPSK), which employs novel digital modem VLSICs. The modulator VLSIC directly generates modulated intermediate frequency (IF) signals in a fully digitalized manner. A newly proposed digital reverse-modulation and pre-filtered carrier filter-limiter scheme realizes low power consumption and stable operation in a low Eb/No condition. The demodulator VLSIC also achieves fast bit-timing acquisition in burst mode. Moreover, it supports stable initial burst acquisition by a novel automatic frequency control (AFC) acquisition detector and a digital burst detector. A digital burst automatic gain control (AGC) compensates burst-to-burst level differences without analog circutits. Performance evaluation results show that the new modem achieves satisfactory bit-error-rate performance in severe environments. The developed modem has been employed in a commercial portable earth station for ISDN services and reduces the hardware size to one third that of the conventional one.

  • Ultra-High-Speed and Universal-Coding-Rate Viterbi Decoder VLSIC--SNUFEC VLSI--

    Katsuhiko KAWAZOE  Shunji HONDA  Shuji KUBOTA  Shuzo KATO  

     
    PAPER-Multimedia System LSIs

      Vol:
    E77-C No:12
      Page(s):
    1888-1894

    An Ultra-high-speed (higher than 60 MHz) Viterbi decoder VLSIC with coding rates from one-half to fifteen-sixteenth and a constraint length of seven for forward error correction (FEC) has been developed using 0.8-µm semicustom CMOS LSIC technology and a newly developed high-speed ACS circuit. To reduce power consumption of the one-chip Viterbi decoder, a universal-coding-rate scarce-state-transition (SST) Viterbi decoding scheme and low-power-consumption burst-mode-selection (BMS) path memory have been proposed and employed to the developed VLSIC. In addition, a new maximum-likelihood-decision (MLD) circuit for the SST Viterbi decoder has been developed. The total power consumption of the developed chip is reduced to 75% of the conventional one and the developed Viterbi decodar VLSIC achieves a maximum operation speed of 60 MHz. It achieves near theoretical net coding-gain performance for various coding rates.