Actuator-induced disturbances are among the most crucial factors in correct spacecraft attitude pointing and stability for fine attitude control problems. In order to develop a CMG as an actuator for fine controls, CMG-induced disturbances should be analyzed. Therefore, this paper aims to develop an analytic model that predicts the effect of disturbances to CMGs by assuming static and dynamic imbalances. The proposed analytical model with respect to the disturbances of a CMG is derived using the Lagrange energy method based on the small-signal assumption.

With the process scaling, the leakage current reduction has been the primary design concerns in a nanometer-era VLSI circuit. In this paper, we propose a new lithography process-aware edge effects correction method to reduce the leakage current in the shallow trench isolation (STI). We construct the various test structures to model Ileakage and Ileakage_fringe which represent the leakage currents at the center and edge of the transistor, respectively. The layout near the active edge is modified using the look-up table generated by the calibrated analytic model. On average, the proposed edge effects correction method reduces the leakage current by 18% with the negligible decrease of the drive current at sub-40nm DRAM device.

Next-generation wireless/mobile networks will be IP-based cellular networks integrating Internet with the existing cellular networks. Recently, Hierarchical Mobile IPv6 (HMIPv6) was proposed by the Internet Engineering Task Force (IETF) for efficient mobility management. HMIPv6 reduces the amount of signaling and improves the performance of MIPv6 in terms of handoff latency. Although HMIPv6 is an efficient scheme, the performance of wireless networks is highly dependent on various system parameters such as user mobility model, packet arrival pattern, etc. Therefore, it is essential to analyze the network performance when HMIPv6 is deployed in IP-based cellular networks. In this paper, we develop two analytic models for the performance analysis of HMIPv6 in IP-based cellular networks, which are based on the random-walk and the fluid-flow models. Based on these analytic models, we formulate the location update cost and the packet delivery cost. Then, we analyze the impact of cell residence time and user population on the location update cost and the packet delivery cost, respectively. In addition, we study the variation of the total cost as the session-to-mobility ratio is changed and the optimal MAP domain size to minimize the total cost is also investigated.

In this paper, we apply the Semi-markov Memory and Cache coherence Interference (SMCI) model, which we had proposed for invalidating based cache coherent parallel computers, to an updating based protocol. The model proposed here, the SMCI/Dragon model, can predict performance of cache coherent parallel computers with the Dragon protocol as well as the original SMCI model for the Synapse protocol. Conventional analytic models by stochastic processes to describe parallel computers have the problem of numerical explosion in the number of states necessary as the system size increases. We have already shown that the SMCI model achieved both the small number of states to describe parallel computers with the Synapse protocol and the inexpensive computation cost to predict their performance. In this paper, we demonstrate generality of the SMCI model by applying it to the another cache coherence protocol, Dragon, which has opposite characteristics than Synapse. We show the number of states required by constructing the SMCI/Dragon model is only 21 which is as small as SMCI/Synapse, and the computation cost is also the order of microseconds. Using the SMCI/Dragon model, we investigate several comparative experiments with widely known simulation results. We found that there is only a 5. 4% differences between the simulation and the SMCI/Dragon model.

UNcorrectable Bit Errors (UNBEs) are important in considering the reliability of Redundant Array of Inexpensive Disks (RAID). They, however, have been ignored or have not been studied in detail in existing reliability analysis of RAID. In this paper, we present an analytic model to study the reliability of declustered-parity RAID by considering UNBEs. By using the analytic model, the optimistic and the pessimistic estimates of the probability that data loss occurs due to an UNBE during the data reconstruction after a disk failed (we call this DB data loss) are obtained. Then, the optimistic and the pessimistic estimates of the Mean Time To Data Loss (MTTDL) that take into account both DB data loss and the data loss caused by double independent disk failures (we call this DD data loss) are obtained. Furthermore, how the MTTDL depends on the number of units in a parity stripe, rebuild time of a failed disk and write fraction of data access are studied by numerical analysis.

In this paper, we propose an analytic model using a semi-markov process for parallel computers which provides hardware support for a cache coherence mechanism. The model proposed here, the Semi-markov Memory and Cache coherence Interference model, can be used for the performance prediction of cache coherence based parallel computers since it can be easily applied to descriptions of the waiting states due to network contention or memory interference of both normal data accesses and cache coherence requests. Conventional analytic models using stochastic processes to describe parallel computers have the problem of numerical explosion in the number of states necessary as the system size increases even for simple parallel computers without cache coherence mechanisms. The number of states required by constructing our proposing analytic model, however, does not depend on the system size but only on the kind of cache coherence protocol. For example, the number of states for the Synapse cache coherence protocol is only 20, as is described in this paper. Using the proposed analytic model, we investigate several comparative experiments with widely known simulation results. We found that there is only a 7.08% difference between the simulation and our analytic model, while our analytic model can predict the performance of a 1,024 processor system in the order of microseconds.