This paper proposes a differentially-coded-quadrature-phase-shift-keying (DQPSK) coherent demodulator using a new simultaneous carrier and bit-timing recovery scheme (SCBR). The new DQPSK SCBR (DSCBR) scheme works with a frequently used preamble, whose baseband signal alternates between two diagonal decision points, for example, a repeated bit-series of "1001." With the DSCBR scheme, the proposed demodulator achieves a significantly agile carrier and bit-timing recovery using an open-loop approach with a one-part preamble. To illustrate this, a preamble of 8 symbols is applicable with the Eb/No degradation from the theory over AWGN of 0.2 dB. It is also shown that the proposed demodulator achieves an improvement in the required Eb/No of more than 2 dB over differential detection over Ricean fading communication channels. The channels are modeled for wireless broadband communication systems with directional antennas or line of sight (LOS) paths. This paper concludes that the proposed demodulator is a strong candidate for receivers in wireles broadband communication systems.

This paper presents a new offset-quadrature-phase-shift-keying (OQPSK) coherent demodulation scheme for wireless asynchronous transfer mode (WATM) systems that premise the Ricean fading communication channels (e.g., typically with derectional antennas). The presented demodulator is basically advanced from a simultaneous carrier and bit-timing recovery (SCBR) scheme by newly employing a phase compensated filter and a reverse-modulation scheme for OQPSK. This advancement aims to enhance the carrier phase tracking performance against the phase fluctuation due to the fading and/or the phase rotation caused by the carrier frequency error of the oscillator. Design consideration and performance evaluation of the demodulator are extensively carried out under Ricean fading channels typical of the WATM systems as well as additive white Gaussian noise (AWGN) channels. The evaluation ressults show that the advanced SCBR (ASCBR) scheme achieves a bit-error-rate/cell-error-rate (BER/CER) performance close to ideal coherent detection with a considerably short preamble, e.g., 8 symbols. Specifically, compared with differential detection (evaluated for QPSK with the hard-wired clock), the new coherent demodulator achieves a significant required Eb/No improvement, which becomes larger as the fading condition degrades. This paper concludes that the ASCBR scheme is a strong candidate for the Ricean-fading-premise WATM systems.

This paper proposes a new simultaneous carrier and bit-timing recovery (CBR) scheme for offset quadrature phase shift keying (O-QPSK) for agile acquisition over satellite communication channels. The proposed simultaneous CBR scheme employs a preamble shared for the carrier and bit-timing recover, which has a specific bit-pattern designed so that its baseband signal alternates between two adjacent decision points at the symbol rate. Using the preamble, the proposed simultaneous CBR scheme estimates the carrier phase and the bit-timing, simultaneously and independently, by open-loop approach. For comparison, this paper also describes the performance and configuration of a joint carrier and bit-timing recovery scheme, which is expanded for O-QPSK from the one conventionally proposed for QPSK. This paper demonstrates with simulation results that the proposed simultaneous CBR scheme significantly improves the agility of acquisition: a mere 30-symbol preamble is sufficient for low-Eb/No channels typical of satellite communication systems. The proposed CBR scheme is also advantageous from the viewpoint of digital implementation: it processes at 2 samples/symbol and eliminates an analog voltage control clock (VCC). The proposed simultaneous CBR scheme is a strong candidate for TDMA systems that require the high data-transmission and frequency utilization efficiency.

This paper presents a fully digital high speed (60 Mb/s) Quadrature Phase Shift Keying (QPSK)/Offset QPSK (OQPSK) burst demodulator for radio applications, which has been implemented on a 0.5 µm Complementary Metal Oxide Semiconductor (CMOS) master slice Very Large Scale Integrated circuit (VLSI). The developed demodulator VLSI eliminates analog devices such as mixers, phase-shifters and Voltage Controlled Oscillator (VCO) for bit-timing recovery, which are used by conventional high-speed burst demodulators. In addition to the fully digital implementation, the VLSI achieves fast carrier and bit-timing acquisition in burst modes by employing a reverse-modulation carrier recovery scheme with a wave-forming filter for OQPSK operation, and a bit-timing recovery scheme with bit-timing estimation and interpolation using a pulse-shaping filter. Results of performance evaluation assuming application in Time Division Multiple Access (TDMA) systems show that the developed VLSI achieves excellent bit-error-rate and carrier-slipping-rate performance at high speed (60 Mb/s) with short preamble words (less than 100 symbols) in low Eb/No environments.