Frequency-domain equalization (FDE) has been studied for suppressing inter-symbol interference (ISI) due to frequency selective fading in single carrier systems. When a high-mobility terminal is assumed in the system, channel transition within an FDE block cannot be ignored. The ISI reduction performance of FDE degrades since the cyclicity of the channel matrix is lost. To solve this problem, a method of dividing the received data block into multiple subblocks has been proposed, where pseudo cyclic prefix (CP) processing is introduced to realize periodicity in each subblock. In this method, the performance is degraded by the inherently-inaccurate pseudo CP. In this paper, we study the application of frequency-domain turbo equalization (FDTE) to subblock processing for improving the accuracy of pseudo CP. The simulation results show that FDTE with subblock processing yields remarkable performance improvements.

The rapid growth of multimedia applications has increased interest in the compression of video data. This paper presents a new method for improving the compression ratio of video data, which can be easily used in a multilayer environment for error resilience applications as well. Data of four luminance blocks in a macroblock are processed and arranged in such a way that important macroblock data is compressed in one block(A), while the rest of the three remaining data blocks(H,V,D) are given difference values in the horizontal, vertical and diagonal directions. This results in a reduced bitstream size because of the low-valued data present in the three blocks(H,V,D), giving better compression at low bitrates. In an error resilient environment, the important data block in a macroblock is transmitted in a secure channel while the remaining three blocks with difference data are sent via a lossy channel. If error occurs in the lossy channel, picture can still be reconstructed with reasonably good quality using only the block data that is transmitted in the secure channel.

This paper treats the problem of realizing high speed 2-D denominator separable digital filters. Partitioning a 2-D data plane into square blocks, filtering proceeds block by block sequentially. A fast intra-block parallel processing method was developed using block state space realization, which allows simultaneous computation of all the next block states and the outputs of one block. As the block state matrix of the filter has high sparsity, the rows and columns are interchanged respectively to reduce the matrix size. The filter is implemented by a multiprocessor system, where for each matrix's row one processor is assigned to perform the row-column vector multiplication. All processors wirk in synchronized fashion. Number of processors of this implementation are equal to the number of rows of the reduced state matrix and throughput is raised with block lengths.