Burn-in is a widely used method to improve the quality of products or systems after they have been produced. In this paper, optimal burn-in procedures for a system with two types of failures (i.e., minor and catastrophic failures) are investigated. A new system surviving burn-in time b is put into field operation and the system is used under a warranty policy under which the manufacturer agrees to provide a replacement system for any system that fails to achieve a lifetime of at least w. Upper bounds for optimal burn-in time minimizing the total expected warranty cost are obtained under a more general assumption on the shape of the failure rate function which includes the bathtub shaped failure rate function as a special case.

Leakage power is predicted to become dominant in the total operation power as the transistor technology gets advanced. Even in the current technology, dramatic increase of leakage power at elevated temperature is a big problem. Burn-in testing, which is typically performed at 125, is facing at difficulties such as throughput degradation or thermal runaway due to increase of leakage power. Reducing leakage power at operation time is essential to solve these problems. We propose a novel approach to make use of an enable signal of a gated-clock technique for reducing active leakage power. A sleep transistor is provided between combinational logic circuits and the ground, and is controlled by the enable signal. When state transitions do not occur in Finite-State-Machines (FSM's), the enable signal becomes low and the state flip-flops keep the data. At the same time, the sleep transistor is turned off so that combinational logic gates are electrically disconnected from the ground to reduce leakage. Simulation results have shown that the proposed scheme reduces active leakage power by 30-60% in 0.18 µm technology. The total power was reduced by 20% at the maximum at 125. It was also found that performance degradation was tolerable for burn-in testing.