Clocked cascade voltage switch logic (C2VSL) circuits with gated feedback were newly designed for synchronous systems. In order to investigate single event transient (SET) effects on the C2VSL circuits, SET effects on C2VSL EX-OR circuits were analyzed using SPICE. Simulation results have indicated that the C2VSL have increased tolerance to SET.

Single event transient (SET) effects on original static cascade voltage switch logic (CVSL) exclusive-OR (EX-OR) circuits have been investigated using SPICE. SET simulation results have confirmed that the static CVSL EX-OR circuits have increased tolerance to SET. The static CVSL EX-OR circuit is more than 200 times harder than the conventional CMOS circuit.