It has become more important to shorten development periods of high performance computer systems and their LSIs. During debugging of computer prototypes, logic designers request very frequent LSI refabrication to change logic circuits and to add some functions in spite of their extensive logic simulation by several GFLOPS supercomputers. To meet these demands, an automated on-chip direct wiring modification system has been developed, which enables wire-cut and via-digging by a precise focused ion beam machine, and via-filling and jumper-writing by a laser CVD machine, directly on pre-redesign (original) chips. This modification system was applied to LSI reworks during the development of Hitachi large scale computers M-880 and S-3800, and contributed to shorten system debugging period by four to six months.

Existing algorithmic debugging methods which can locate faults under the guidance of a system have a number of shortcomings. For example, some cannot be applied to imperative languages with side effects; some can locate a faulty function but cannot locate a faulty statement; and some cannot detect faults related to missing statements. This paper presents an algorithmic critical slice-based fault-locating method for imperative languages. Program faults are first classified into two categories: wrong-value faults and missing-assignment faults. The critical slice with respect to a variable-value error is a set of statements such that (1) a wrong-value fault contained in any instruction in the critical slice may have caused that variable-value error, and (2) a wrong-value fault contained in any instruction outside the critical slice could never have caused that variable-value error. The paper also classifies errors found during program testing into three categories: wrong-output errors, missing-output errors, and infinite-loop errors with no output. It finally shows that it is possible to algorithmically locate any fault, including missing statements, for each type of error.

Actual debugging actions during the testing phase in the software development and the operation phase are not always performed perfectly. In other words, all detected software faults are not corrected and removed certainly. Generally, this is called imperfect debugging. In this paper, we discuss a software reliability growth model considering imperfect debugging that faults are not always corrected/removed when they are detected. Defining a random variable representing the cumulative number of faults corrected up to a specified testing time, this model is described by a semi-Markov process. We derive various quantitative measures for software reliability assessment and show their numercal examples.