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[Keyword] delta-sigma digital-to-analog converter(2hit)

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  • A Multi-Stage Second Order Dynamic Element Matching with In-Band Mismatch Noise Reduction Enhancement

    Yu TAMURA  Toru IDO  Kenji TANIGUCHI  

     
    BRIEF PAPER-Electronic Circuits

      Vol:
    E94-C No:8
      Page(s):
    1340-1343

    This paper presents a technique to enhance in-band mismatch noise reduction of multi-stage second order Dynamic Element Matching (DEM) in multi-level ΔΣ Digital-to-Analog Converters (DACs). The presented technique changes an operational behavior of multi-stage DEM to reduce mismatch noise at in-band frequency. This change improves mismatch noise shaping performance for small amplitude input signals. Simulation result using 2-stage second order DEM and a third order 17-level ΔΣ modulator with 0.5% analog element mismatch shows 3.4 dB dynamic range improvement.

  • A Dynamic Dither Gain Control Technique for Multi-Level Delta-Sigma DACs with Multi-Stage Second Order Dynamic Element Matching

    Yu TAMURA  Toru IDO  Kenji TANIGUCHI  

     
    PAPER-Electronic Circuits

      Vol:
    E94-C No:3
      Page(s):
    346-352

    A dynamic dither gain control technique for multi-level delta-sigma Digital-to-Analog Converters (DACs) using multi-stage Dynamic Element Matching (DEM) with a second order loop filter is proposed. The proposed technique provides improvement on the mismatch shaping performance through dynamic control of delta-sigma modulator dither gain. A large dither gain, which suppresses DEM operation dependency on input signal, is applied to delta-sigma modulator, when DEM loop filter output is greater than a designed reference. The design example using the proposed technique on a third order 17-level delta-sigma modulator with 3-stage cascaded DEM is shown in this paper. Simulation result with 1% analog segment mismatch shows over 10 dB improvement of THD+N performance under -50 dB amplitude input signal, compared to the case without the proposed technique.