A hinge vertex is a vertex in an undirected graph such that there exist two vertices whose removal makes the distance between them longer than before. Identifying hinge vertices in a graph can help detect critical nodes in communication network systems, which is useful for making them more stable. For finding them, an O(n3) time algorithm was developed for a simple graph, and, linear time algorithms were developed for interval and permutation graphs, respectively. Recently, the maximum detour hinge vertex problem is defined by Honma et al. For a hinge vertex u in a graph, the detour degree of u is the largest value of distance between any pair of x and y (x and y are adjacent to u) by removing u. A hinge vertex with the largest detour degree in G is defined as the maximum detour hinge vertex of G. This problem is motivated by practical applications, such as network stabilization with a limited cost, i.e., by enhancing the reliability of the maximum detour hinge vertex, the stability of the network is much improved. We previously developed an O(n2) time algorithm for solving this problem on an interval graph. In this study, we propose an algorithm that identifies the maximum detour hinge vertex on a permutation graph in O(n2) time, where n is the number of vertices in the graph.

Consider a simple undirected graph G = (V,E) with vertex set V and edge set E. Let G-u be a subgraph induced by the vertex set V-{u}. The distance δG(x,y) is defined as the length of the shortest path between vertices x and y in G. The vertex u ∈ V is a hinge vertex if there exist two vertices x,y ∈ V-{u} such that δG-u(x,y)>δG(x,y). Let U be a set consisting of all hinge vertices of G. The neighborhood of u is the set of all vertices adjacent to u and is denoted by N(u). We define d(u) = max{δG-u(x,y) | δG-u(x,y)>δG(x,y),x,y ∈ N(u)} for u ∈ U as detour degree of u. A maximum detour hinge vertex problem is to find a hinge vertex u with maximum d(u) in G. In this paper, we proposed an algorithm to find the maximum detour hinge vertex on an interval graph that runs in O(n2) time, where n is the number of vertices in the graph.

Given a simple connected graph G with n vertices, the spanning tree problem involves finding a tree that connects all the vertices of G. Solutions to this problem have applications in electrical power provision, computer network design, circuit analysis, among others. It is known that highly efficient sequential or parallel algorithms can be developed by restricting classes of graphs. Circular trapezoid graphs are proper superclasses of trapezoid graphs. In this paper, we propose an O(n) time algorithm for the spanning tree problem on a circular trapezoid graph. Moreover, this algorithm can be implemented in O(log n) time with O(n/log n) processors on EREW PRAM computation model.

Let Gs=(Vs, Es) be a simple connected graph. A vertex v ∈ Vs is an articulation vertex if deletion of v and its incident edges from Gs disconnects the graph into at least two connected components. Finding all articulation vertices of a given graph is called the articulation vertex problem. A vertex u ∈ Vs is called a hinge vertex if there exist any two vertices x and y in Gs whose distance increase when u is removed. Finding all hinge vertices of a given graph is called the hinge vertex problem. These problems can be applied to improve the stability and robustness of communication network systems. In this paper, we propose linear time algorithms for the articulation vertex problem and the hinge vertex problem of circular permutation graphs.

In an undirected graph, the feedback vertex set (FVS for short) problem is to find a set of vertices of minimum cardinality whose removal makes the graph acyclic. The FVS has applications to several areas such that combinatorial circuit design, synchronous systems, computer systems, VLSI circuits and so on. The FVS problem is known to be NP-hard on general graphs but interesting polynomial solutions have been found for some special classes of graphs. In this paper, we present an O(n2.68 + γn) time algorithm for solving the FVS problem on trapezoid graphs, where γ is the total number of factors included in all maximal cliques.

Packet concentrators are used in many high-speed computer communication systems such as fast packet switches. In these systems, the time available for concentration is very short. It is therefore desirable to realize the packet concentrators as hardware chips for fast concentration. The knockout concentrator was proposed for hardware realization. In this paper, we improve this concentrator to reduce the probability of packet loss, and the improved concentrator is called wraparound knockout concentrator. This concentrator has several wraparound paths within it, and it does not require any additional pin per chip. After contention among the packets in a slot, each winner goes to a distinct output, some losers circulate along the wraparound paths for contention in the subsequent slot, and the remaining losers are discarded. In this manner, some losers are not discarded immediately and they still have the chance to go to the outputs in the subsequent slot, thereby reducing the probability of packet loss. We analyze the number of logic gates required and the probability of packet loss. The numerical results show that if the proposed concentrator has a few wraparound paths, the probability of packet loss can already be reduced by orders of magnitude.

The EMC-adequate design of microelectronic systems includes all actions intended to eliminate electromagnetic interference in electronic systems. Challenges faced in the microelectronic area include a growing system complexity, high integration levels and higher operating speeds at all levels of integration (chip, MCM, printed circuit board and system). The growing complexity, denser design and higher speed all lead to a substantial increase in EMC problems and accordingly the design time. EMC is not commonly accepted as a vital topic in microelectronic design. Microelectronic designers often are of the opinion that EMC is limited to electrical and electronic systems and the mandatory product regulations instead of setting requirements also for the integrated circuit they are designing. In this contribution a concept for an EMC-adequate design of electronic systems will be introduced. This concept is based on a generalized development process to integrate EMC-constraints into the system design. A prototype of an environment to analyse signal integrity effects on PCB based on a workflow oriented integration approach will be presented. Based on this approach the generation of user specific design and analysis environments including various set of EMC-tools is possible.