In this paper, a novel orthogonal frequency-division multiplexing (OFDM) modulator/demodulator based on real-valued discrete Hartley transform (DHT) is presented and implemented for the IEEE 802.11a/g wireless local area network (LAN). Instead of the conventional complex-valued fast Fourier transform (FFT) for OFDM systems, the proposed architecture employs two real-valued fast DHT (FHT) kernels and one post processing unit. By taking advantage of the real-valued operation of FHT, this approach reduces the number of multiplications compared with the radix-2 FFT. The proposed DHT-based modulator/demodulator was designed and fabricated in 0.18-µm CMOS technology with a core area of 928935 µm2. The average power consumption is about 20.16 mW at 20 MHz and 1.8 V supply voltage. Measurement results of the integrated circuit illustrate its superior chip area and power consumption.

In this paper, the 1-D real-valued discrete Gabor transform (RDGT) proposed in our previous work and its relationship with the complex-valued discrete Gabor transform (CDGT) are briefly reviewed. Block time-recursive RDGT algorithms for the efficient and fast computation of the 1-D RDGT coefficients and for the fast reconstruction of the original signal from the coefficients are then developed in both the critical sampling case and the oversampling case. Unified parallel lattice structures for the implementation of the algorithms are studied. And the computational complexity analysis and comparison show that the proposed algorithms provide a more efficient and faster approach for the computation of the discrete Gabor transforms.

This paper presents a long length discrete Hartley transform (DHT) design with a new hardware efficient distributed arithmetic (DA) approach. The new DA design approach not only explores the constant property of coefficients as the conventional DA, but also exploits its cyclic property. To efficiently apply this approach to long length DHT, we first decompose the long length DHT algorithm to short ones using the prime factor algorithm (PFA), and further reformulate it by using Agarwal-Cooley algorithm such that all the partitioned short DHT still consists of the cyclic property. Besides, we also exploit the scheme of computation sharing on the content of ROM to reduce the hardware cost with the trade-off in slowing down the computing speeds. Comparing with the existing designs shows that the proposed design can reduce the area-delay product from 52% to 91% according to a 0.35 µm CMOS cell library.