IEICE TRANSACTIONS on Electronics
The Long Length DHT Design with a New Hardware Efficient Distributed Arithmetic Approach and Cyclic Preserving Partitioning
Summary :
This paper presents a long length discrete Hartley transform (DHT) design with a new hardware efficient distributed arithmetic (DA) approach. The new DA design approach not only explores the constant property of coefficients as the conventional DA, but also exploits its cyclic property. To efficiently apply this approach to long length DHT, we first decompose the long length DHT algorithm to short ones using the prime factor algorithm (PFA), and further reformulate it by using Agarwal-Cooley algorithm such that all the partitioned short DHT still consists of the cyclic property. Besides, we also exploit the scheme of computation sharing on the content of ROM to reduce the hardware cost with the trade-off in slowing down the computing speeds. Comparing with the existing designs shows that the proposed design can reduce the area-delay product from 52% to 91% according to a 0.35 µm CMOS cell library.
- Publication
- IEICE TRANSACTIONS on Electronics Vol.E88-C No.5 pp.1061-1069
- Publication Date
- 2005/05/01
- Publicized
- Online ISSN
- DOI
- 10.1093/ietele/e88-c.5.1061
- Type of Manuscript
- PAPER
- Category
- Electronic Circuits
Authors
Keyword
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Hun-Chen CHEN, Tian-Sheuan CHANG, Jiun-In GUO, Chein-Wei JEN, "The Long Length DHT Design with a New Hardware Efficient Distributed Arithmetic Approach and Cyclic Preserving Partitioning" in IEICE TRANSACTIONS on Electronics,
vol. E88-C, no. 5, pp. 1061-1069, May 2005, doi: 10.1093/ietele/e88-c.5.1061.
Abstract: This paper presents a long length discrete Hartley transform (DHT) design with a new hardware efficient distributed arithmetic (DA) approach. The new DA design approach not only explores the constant property of coefficients as the conventional DA, but also exploits its cyclic property. To efficiently apply this approach to long length DHT, we first decompose the long length DHT algorithm to short ones using the prime factor algorithm (PFA), and further reformulate it by using Agarwal-Cooley algorithm such that all the partitioned short DHT still consists of the cyclic property. Besides, we also exploit the scheme of computation sharing on the content of ROM to reduce the hardware cost with the trade-off in slowing down the computing speeds. Comparing with the existing designs shows that the proposed design can reduce the area-delay product from 52% to 91% according to a 0.35 µm CMOS cell library.
URL: https://global.ieice.org/en_transactions/electronics/10.1093/ietele/e88-c.5.1061/_p
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@ARTICLE{e88-c_5_1061,
author={Hun-Chen CHEN, Tian-Sheuan CHANG, Jiun-In GUO, Chein-Wei JEN, },
journal={IEICE TRANSACTIONS on Electronics},
title={The Long Length DHT Design with a New Hardware Efficient Distributed Arithmetic Approach and Cyclic Preserving Partitioning},
year={2005},
volume={E88-C},
number={5},
pages={1061-1069},
abstract={This paper presents a long length discrete Hartley transform (DHT) design with a new hardware efficient distributed arithmetic (DA) approach. The new DA design approach not only explores the constant property of coefficients as the conventional DA, but also exploits its cyclic property. To efficiently apply this approach to long length DHT, we first decompose the long length DHT algorithm to short ones using the prime factor algorithm (PFA), and further reformulate it by using Agarwal-Cooley algorithm such that all the partitioned short DHT still consists of the cyclic property. Besides, we also exploit the scheme of computation sharing on the content of ROM to reduce the hardware cost with the trade-off in slowing down the computing speeds. Comparing with the existing designs shows that the proposed design can reduce the area-delay product from 52% to 91% according to a 0.35 µm CMOS cell library.},
keywords={},
doi={10.1093/ietele/e88-c.5.1061},
ISSN={},
month={May},}
Copy
TY - JOUR
TI - The Long Length DHT Design with a New Hardware Efficient Distributed Arithmetic Approach and Cyclic Preserving Partitioning
T2 - IEICE TRANSACTIONS on Electronics
SP - 1061
EP - 1069
AU - Hun-Chen CHEN
AU - Tian-Sheuan CHANG
AU - Jiun-In GUO
AU - Chein-Wei JEN
PY - 2005
DO - 10.1093/ietele/e88-c.5.1061
JO - IEICE TRANSACTIONS on Electronics
SN -
VL - E88-C
IS - 5
JA - IEICE TRANSACTIONS on Electronics
Y1 - May 2005
AB - This paper presents a long length discrete Hartley transform (DHT) design with a new hardware efficient distributed arithmetic (DA) approach. The new DA design approach not only explores the constant property of coefficients as the conventional DA, but also exploits its cyclic property. To efficiently apply this approach to long length DHT, we first decompose the long length DHT algorithm to short ones using the prime factor algorithm (PFA), and further reformulate it by using Agarwal-Cooley algorithm such that all the partitioned short DHT still consists of the cyclic property. Besides, we also exploit the scheme of computation sharing on the content of ROM to reduce the hardware cost with the trade-off in slowing down the computing speeds. Comparing with the existing designs shows that the proposed design can reduce the area-delay product from 52% to 91% according to a 0.35 µm CMOS cell library.
ER -
English
