3G must offer high data rates since it should support real-time multimedia services; one performance enhancement, the use of the OVSF code tree, has adopted in 3G WCDMA networks. Unfortunately, this technique allows the link capacity to be set at the base rate times powers of two. This results in wasting bandwidth while the required rate is not powers of two of the basic rate. Several multi-code assignment mechanisms have been proposed to reduce the waste rate, but incur some drawbacks, including high complexity of handling multiple codes and increasing cost of using more rake combiners. Our solution is a dynamic grouping code assignment that allows any rate to be achieved with a single code for any possible rate of traffic. The dynamic grouping approach first forms several calls into a group. It then allocates a subtree to the group and dynamically shares the subtree codes based on time-sharing of slots within a group cycle time. The waste rate and code blocking is thus reduced significantly. Since transmission delay and jitter may occur in such a time-sharing approach, two schemes of cycle interleaving are proposed to minimize delay and jitter. Numerical results demonstrate that the proposed approach reduces the waste rate and increases the system utilization obviously, and the proposed cycle interleaving schemes minimizes delay and jitter significantly.

In this paper, we propose an efficient IP-Level power model with a small lookup table for complex CMOS circuits. The table has only one dimension that maps the zero-delay charging and discharging capacitance (CDC) into the real power consumption of pattern pairs but still has high accuracy. In order to reduce the table size, we collect those pattern pairs with similar CDC values to be a group and only set an entry in the lookup table for each group. The proposed dynamic grouping process can automatically increase the entries of the lookup tables to cover the current CDC distribution of designs during the power characterization process. In order to improve the efficiency of characterization process, the Monte Carlo approach is used during the estimation for the average power of each group to skip the samples that will not increase the accuracy too much. After the power model of a circuit is built, the average power consumption for any test sequence can be estimated easily. The experimental result shows that the table sizes are only up to 107 entries for ISCAS'85 benchmark circuits and the estimation error is only 2.99% on average using this lookup table.