In this paper, a macro cell switching scheme for distributed antennas is proposed. In conventional distributed antenna transmission (DAT), the macro cell to which each antenna belongs is fixed. Though a cell-free system has been investigated because of its higher system throughput, the implementation cost of front-hauls can be excessive. To increase the flexibility of resource allocation in the DAT with moderate front-haul complexity, we propose the macro cell switching of distributed antennas (DAs). In the proposed scheme, DAs switch their attribution macro cells depending on the amount of pre-assigned connections. Numerical results obtained through computer simulation show that the proposed scheme realizes a better system throughput than the conventional system, especially when the number of user equipments (UEs) is smaller and the distance between DAs are larger.

In femto/macro cellular networks, the stability and fairness problems caused by the unplanned and random characteristic of femtocells must be solved. By applying queueing theory in IP based femto/macro cellular networks, we found the stability condition, and described two kinds of cell section policies of users. As a main contribution, we provided the adaptive channel distribution algorithm which minimizes the average packet sojourn time at transmitting systems and keeps the whole systems stable and fair among cells. Through experiments in various environments, we analyzed the influence of channel reuse factor, cell selection policies, and the number of femtocells on system performance.

Pitchmatching algorithms are widely used in layout environments where no grid constraints are imposed. However, realistic layouts include multiple grid constraints which facilitate the applications of automatic routing. Hence, pitchmatching algorithms should be extended to those realistic layouts. This paper formulates a pitchmatching problem with multiple grid constraints. An algorithm for solving this problem is constructed as an extension of conventional pitchmatching algorithms. The computational complexity is also discussed in comparison with a conventional naive algorithm. Finally, examples and application results to realistic layouts are presented.

This paper describes a new automated approach to generating the patterns of CMOS leaf cells from transistor-level connectivity data. This method can generate CMOS leaf cells that are configurable to a macro cell satisfying user-specified constraints. The user-specified constraints include the aspect ratio and port positions of the macro cell. We propose a top-down method for converting the macro cell level constratints to leaf cell level ones. Using this method, a variety of customized macro cells can be designed in a short turn-around time. The method consists of four processes--diffusion sharing, initial placement, placement improvement and routing--which culminate in the automatic generation of symbolic representations. Using a compactor, those symbolic representations can be converted to physical patterns which are gathered into a macro cell by a macro generator. We define various objective functions to improve unit pair placement. We also introduce five ways to optimize leaf cell area: 1) multi-row division, 2) gate division 3) rotation, 4) power line and diffusion overlapping and 5) reconstruction of hierarchical structure. The proposed approach has been applied to various kinds of CMOS leaf cells. Experimental results show that the generated cells have almost the same areas as those generated by conventional bottom-up approaches in leaf and macro cell layouts. This approach offers a further advantage in that the various-sized macro cells required by layout disigners can also be generated.

In this paper, we propose a new algorithm for the problem of floorplanning of the mixed design of macro and standard cells. The proposed algorithm which is based on partitioning and slicing approach, uses a modified min-cut bipartitioning heuristic. The heuristic bipartitions a block of a mixture of macro and standard cells to minimize the netcut, which are the number of nets connecting both sub-blocks, with size constraints. A sub-block is a resulting descendant block. Before starting the bipartitioning of the block, the macro cell with the longest side in the block is selected first. Using edges of the selected macro cell, bipartitionings are performed twice fixing the location of the macro cell on one of 4 corners of the block with its rotation and reflection. Bipartitioning of blocks is repeated until each block has either a macro cell or standard cells without macro cells. As a result of bipartitioning, a slicing tree is constructed. Using the proposed floorplan algorithm, we developed an automatic placement and routing tool, Cell Designer, for the mixed design of macro and standard cells. According to the floorplanner, macro cells are placed and standard cells are grouped into standard cell blocks. Standard cells are placed and routed within estimated area of block using conventional tools. They form a fixed-shaped block like a macro cell. Interconnections between the two adjacent blocks are performed with a conventional channel router. The channels and the order of channel routing are determined following the hierarchy of the slicing tree. Cell Designer has a dedicated graphics editor to provide interactive services to users. Experimental results on well-known benchmark data are shown.