Scale Invariant Feature Transform (SIFT) algorithm is a very excellent approach for feature detection. It is characterized by data intensive computation. The current studies of accelerating SIFT algorithm are mainly reflected in three aspects: optimizing the parallel parts of the algorithm based on general-purpose multi-core processors, designing the customized multi-core processor dedicated for SIFT, and implementing it based on the FPGA platform. The real-time performance of SIFT has been highly improved. However, the factors such as the input image size, the number of octaves and scale factors in the SIFT algorithm are restricted for some solutions, the flexibility that ensures the high execution performance under variable factors should be improved. This paper proposes a reconfigurable solution to solve this problem. We fully exploit the algorithm and adopt several techniques, such as full parallel execution, block computation and CORDIC transformation, etc., to improve the execution efficiency on a REconfigurable MUltimedia System called REMUS. Experimental results show that the execution performance of the SIFT is improved by 33%, 50% and 8 times comparing with that executed in the multi-core platform, FPGA and ASIC separately. The scheme of dynamic reconfiguration in this work can configure the circuits to meet the computation requirements under different input image size, different number of octaves and scale factors in the process of computing.

REMUS-II (REconfigurable MUltimedia System 2) is a coarse-grained dynamically reconfigurable computing system for multimedia and communication baseband processing. This paper proposes a real-time H.264 baseline profile encoder on REMUS-II. First, we propose an overall mapping flow for mapping algorithms onto the platform of REMUS-II system and then illustrate it by implementing the H.264 encoder. Second, parallel and pipelining techniques are considered for fully exploiting the abundant computing resources of REMUS-II, thus increasing total computing throughput and solving high computational complexity of H.264 encoder. Besides, some data-reuse schemes are also used to increase data-reuse ratio and therefore reduce the required data bandwidth. Third, we propose a scheduling scheme to manage run-time reconfiguration of the system. The scheduling is also responsible for synchronizing the data communication between tasks and handling conflict between hardware resources. Experimental results prove that the REMUS-MB (REMUS-II version for mobile applications) system can perform a real-time H.264/AVC baseline profile encoder. The encoder can encode CIF@30 fps video sequences with two reference frames and maximum search range of [-16,15]. The implementation, thereby, can be applied to handheld devices targeted at mobile multimedia applications. The platform of REMUS-MB system is designed and synthesized by using TSMC 65 nm low power technology. The die size of REMUS-MB is 13.97 mm2. REMUS-MB consumes, on average, about 100 mW while working at 166 MHz. To my knowledge, in the literature this is the first implementation of H.264 encoding algorithm on a coarse-grained dynamically reconfigurable computing system.

This paper introduces a cycle-accurate Simulator for a dynamically REconfigurable MUlti-media System, called SimREMUS. SimREMUS can either be used at transaction-level, which allows the modeling and simulation of higher-level hardware and embedded software, or at register transfer level, if the dynamic system behavior is desired to be observed at signal level. Trade-offs among a set of criteria that are frequently used to characterize the design of a reconfigurable computing system, such as granularity, programmability, configurability as well as architecture of processing elements and route modules etc., can be quickly evaluated. Moreover, a complete tool chain for SimREMUS, including compiler and debugger, is developed. SimREMUS could simulate 270 k cycles per second for million gates SoC (System-on-a-Chip) and produced one H.264 1080p frame in 15 minutes, which might cost days on VCS (platform: CPU: E5200@ 2.5 Ghz, RAM: 2.0 GB). Simulation showed that 1080p@30 fps of H.264 High Profile@ Level 4 can be achieved when exploiting a 200 MHz working frequency on the VLSI architecture of REMUS.

This paper proposes approaches to perform HW/SW (Hardware/Software) partition and parallelization of computing-intensive tasks of the H.264 HiP (High Profile) decoding algorithm on an embedded coarse-grained reconfigurable multimedia system, called REMUS (REconfigurable MUltimedia System). Several techniques, such as MB (Macro-Block) based parallelization, unfixed sub-block operation etc., are utilized to speed up the decoding process, satisfying the requirements of real-time and high quality H.264 applications. Tests show that the execution performance of MC (Motion Compensation), deblocking, and IDCT-IQ (Inverse Discrete Cosine Transform-Inverse Quantization) on REMUS is improved by 60%, 73%, 88.5% in the typical case and 60%, 69%, 88.5% in the worst case, respectively compared with that on XPP PACT (a commercial reconfigurable processor). Compared with ASIC solutions, the performance of MC is improved by 70%, 74% in the typical and in the worst case, respectively, while those of Deblocking remain the same. As for IDCT_IQ, the performance is improved by 17% no matter in the typical or worst case. Relying on the proposed techniques, 1080p@30 fps of H.264 HiP@ Level 4 decoding could be achieved on REMUS when utilizing a 200 MHz working frequency.

This letter introduces a cost-effective chrominance compensation scheme. The proposed method is applied to both 'INTER 1616' and 'SKIP' modes in only anchor P-pictures. By testing using JVT common test condition, simulation results show that proposed method can obtain average BD-PSNR gains for U and V as 0.14 dB and 0.13 dB, respectively while maintaining almost the same BD-PSNR's for Y. For the range of low bit-rate, it is observed that average BD-PSNR gains for Y, U and V are 0.14 dB, 0.49 dB and 0.53 dB, respectively. Necessary computational complexity is very marginal because the number of anchor P-pictures is very small in comparison with whole coded video sequences. However it can be found that the proposed method can significantly improve the coding efficiencies of color components.

This paper introduces an adaptive GOP structure (AGS), which adaptively defines the GOP structure according to the time-varying temporal properties of video sequences, and thus improves the coding efficiency of the MPEG & ITU-T's Joint Scalable Video Coding (JSVC) scheme, the method proposed in this paper, which adaptively modifies the size of GOP based on the image characteristics of video sequence, improves the coding efficiency up to 0.77 dB compared to the JSVC JSVM (Joint Scalable Video Model).

An H.264-based selective FGS coding scheme is proposed. It selectively uses the interframe-prediction data inside the enhancement-layer only when those data can significantly reduce the temporal-redundancies. Since this minimizes the drift effects, the overall coding efficiency is improved. Simulations show that average PSNR of the proposed scheme is higher by 1-3 dB and 3-5 dB than those of the H.264-based FGS and the MPEG-4 video FGS profile, respectively.

With reference to video motion estimation in the framework of the new H.264/AVC video coding standard, this paper presents algorithmic and architectural solutions for the implementation of context-aware coprocessors in real-time, low-power embedded systems. A low-complexity context-aware controller is added to a conventional Full Search (FS) motion estimation engine. While the FS coprocessor is working, the context-aware controller extracts from the intermediate processing results information related to the input signal statistics in order to automatically configure the coprocessor itself in terms of search area size and number of reference frames; thus unnecessary computations and memory accesses can be avoided. The achieved complexity saving factor ranges from 2.2 to 25 depending on the input signal while keeping unaltered performance in terms of motion estimation accuracy. The increased efficiency is exploited both for (i) processing time reduction in case of software implementation on a programmable platform; (ii) power consumption reduction in case of dedicated hardware implementation in CMOS technology.

This paper introduces the water ring scan method especially designed for the scalable video coding schemes such as fine granularity scalabilities (FGS) on the basis of MPEG-4 part-2 and the H.264. The proposed scanning method can improve the subjective quality of the decoded video by most-preferentially encoding, transmitting and decoding the image information of the region of interest. From the various simulation results of FGS coding schemes with MPEG-4 part 2 and H.264, the proposed scanning method can improve the subjective picture quality about 0.5 dB 3.5 dB better than the widely used raster scan order, especially on the region of interest, without significant loss of the quality in the left-over region.

This paper introduces a new frame-based bit-rate control scheme for bandwidth-adaptive video coding. Proposed method can accurately adapt to the rapid varying scene characteristics by reducing the number of occurrences of the extrapolations while updating the rate-distortion model used for determine the appropriate quantization steps.

The (cinema) caption processing that adds descriptive text on a sequence of frames is an important video manipulation function that a video editor should support. This paper proposes an efficient MC-DCT compressed domain approach to insert the caption into the MPEG compressed video stream. It basically adds the DCT blocks of the caption image to the corresponding DCT blocks of the input frames one by one in the MC-DCT domain as in [6]. However, the strength of the caption image is adjusted in the DCT domain to prevent the resulting DCT coefficients from exceeding the maximum value allowed in MPEG. In order to adjust the strength of the caption image adaptively we need to know the exact pixel value of the input image. This is a difficult task in DCT domain. We propose an approximation scheme for the pixel values in which the DC value of a block is used as the expected pixel value for all pixels in that block. Although this approximation may lead to some errors in the caption area, it still provides a relatively high image quality in the non-caption area, whereas the processing time is about 4.9 times faster than the decode-captioning-reencode method.

File system buffers provide memory space for data being transferred to and from disk and act as caches for the recently used blocks, and the buffer manager usually reads ahead data blocks to minimize the number of disk accesses. However, if several multimedia files with different consumption rates are accessed simultaneously from the file system in which LRU buffer replacement strategy is used, the read-ahead blocks of the low rate file are unloaded from memory to be used for loading a data block of a high data rate file, therefore they should be reloaded again into memory from disk when these blocks are actually referenced. This paper proposes and implements a new buffer cache management scheme for a multimedia file system and analyzes the performance of the proposed scheme by modifying the file system kernel of FreeBSD. In this proposed scheme, initially, some buffers are allocated to each opened multimedia file, privately, then these buffers are reused for other data blocks of that file when they are loaded from the disk. Moreover, the number of private buffers allocated for the file is dynamically adjusted according to its data rate. An admission control scheme is also proposed to prevent opening of a new file which may cause overloads in the file system. Experimental results comparing proposed scheme with the original FreeBSD and a simple CTL-based model show that the proposed buffer management scheme could support the realtime play back of several multimedia files with various data rates concurrently without helps of a realtime CPU and disk scheduling.

The concept of controlled resource sharing and dynamic quality of service (QoS) on the next generation Internet has attracted much attention recently. It is suggested that, by imposing real-time revision of shared resource allocated to individual media streams or data flows according to user/application QoS demand and resource availability, more balanced and efficient multimedia services can be provided. In this paper, we present an Adaptive Control Framework (ACF), which is developed for controlled resource sharing and dynamic QoS in real-time multimedia service. We discuss main elements of ACF including 1) Control schemes applicable in the framework, and 2) Control mechanisms used in ACF. It is clearly shown in this paper that, with control schemes and mechanisms incorporated in ACF and supportive algorithms and protocols for ACF applications on the Internet, more flexible service and better overall performance in terms of packet loss, latency, signal-noise ratio and re-synchronization delay, can be offered.

This paper proposes a bitstream scaling technique for MPEG video for the purpose of media synchronizations. The proposed scaling technique can reduce the frame rate as well as the bit rate of an MPEG data sequence to fit them to the values specified by a synchronization system. The advantage of the proposed technique over existing scaling methods is that it is considering not only the performance of synchronization but also the picture quality of the resulting sequences. To further improve the quality of sequences scaled by the proposed method, this paper also proposes an MPEG encoding technique which sets some of the parameters suitable for the scaling. An experiment using these techniques in an actual media synchronization system has illustrated the usefulness of the proposed approach.