An optimized low-power optical memory access network is proposed to alleviate the cost of microring resonators (MRs) in kilocore systems, such as the pass-by loss and integration difficulty. Compared with traditional electronic bus interconnect, the proposed network reduces power consumption and latency by 80% to 89% and 21% to 24%. Moreover, the new network decreases the number of MRs by 90.6% without an increase in power consumption and latency when making a comparison with Optical Ring Network-on-Chip (ORNoC).

With the development of silicon-based Nano-photonics, Optical Network on Chip (ONoC) is, due to its high bandwidth and low latency, becoming an important choice for future multi-core networks. As a key ONoC technology, the arbitration scheme should provide differential arbitration service with high throughput and low latency for various types and priorities of traffic in CMPs. In this work, we propose a fast hierarchical arbitration scheme based on multi-level priority QoS. First, given multi-priority data buffer queue, arbiters provide differential transmissions with fair service for all nodes and guarantee the max-transmit-delay and min-communication-bandwidth for all queues. Second, arbiter adopts the transmit bound resource reservation scheme to reserve time slots for all nodes fairly, thereby achieving a throughput of 100%. Third, we propose fast arbitration with a layout of fast optical arbitration channels (FOACs) to reduce the arbitration period, thereby reducing packet transmitting delay. Simulation results show that with our hierarchical arbitration scheme, all nodes are allocated almost equal service access probability under various traffic patterns; thus, the min-communication-bandwidth and max-transmit-delay is guaranteed to be 5% and 80 cycles, respectively, under the overload demands. This scheme improves throughput by 17% compared to FeatherWeight under a self-similar traffic pattern and decreases arbitration delay by 15% compare to 2-pass arbitration, incurring a total power overhead of 5%.

Optical Network-on-Chip (ONoC) is a promising emerging technology, which can solve the bottlenecks faced by electrical on-chip interconnection. However, the existing proposals of ONoC are mostly built on fixed topologies, which are not flexible enough to support various applications. To make full use of the limited resource and provide a more efficient approach for resource allocation, RONoC (Reconfigurable Optical Network-on-Chip) is proposed in this letter. The topology can be reconfigured to meet the requirement of different applications. An 8×8 nonblocking router is also designed, together with the communication mechanism. The simulation results show that the saturation load of RONoC is 2 times better than mesh, and the energy consumption is 25% lower than mesh.