The search functionality is under construction.
The search functionality is under construction.

Keyword Search Result

[Keyword] parasitic effect(2hit)

1-2hit
  • Evolutionary Synthesis of Practical Filters with Improved Group Delay Response

    Hao-Sheng HOU  Hui-Min HUANG  

     
    LETTER-Electronic Circuits

      Vol:
    E91-C No:9
      Page(s):
    1520-1524

    In this letter, a genetic programming method is used to synthesize filters. In order to improve the group delay characteristics, we propose a novel two-stage fitness function reflecting not only the frequency response but also the group delay characteristics of the evolved filters. We also deal with two practical design considerations, i.e., the filters include parasitic effects and are composed of elements with discrete values. The proposed method is applied to low-pass filter design cases. The experimental results show the method can effectively generate filters satisfying the design considerations and possessing improved group delay characteristics when compared with traditional filters.

  • Parasitic Effects in Multi-Gate MOSFETs

    Yusuke KOBAYASHI  C. Raghunathan MANOJ  Kazuo TSUTSUI  Venkanarayan HARIHARAN  Kuniyuki KAKUSHIMA  V. Ramgopal RAO  Parhat AHMET  Hiroshi IWAI  

     
    PAPER-Integrated Electronics

      Vol:
    E90-C No:10
      Page(s):
    2051-2056

    In this paper, we have systematically investigated parasitic effects due to the gate and source-drain engineering in multi-gate transistors. The potential impact of high-K dielectrics on multi-gate MOSFETs (MuGFETs), such as FinFET, is evaluated through 2D and 3D device simulations over a wide range of proposed dielectric values. It is observed that introduction of high-K dielectrics will significantly degrade the short channel effects (SCEs), however a combination of oxide and high-K stack can effectively control this degradation. The degradation is mainly due to the increase in the internal fringe capacitance coupled with the decrease in gate-channel capacitance. From the circuit perspective, an optimum K value has been identified through mixed mode simulations. Further, as a part of this work, the importance of optimization of the shape of the spacer region is highlighted through full 3D simulations.