Configurable clock is necessary for many applications such as digital communication systems, however, using the conventional direct digital frequency synthesizer (DDS) as a pulse or clock generator may cause jitter problems. People usually employ phase-interpolation approaches to generate a pulse or clock with correct time intervals. This work proposes a new phase-interpolation DDS scheme, which uses the output of the phase accumulator to provide an initial voltage on an integration capacitor by pre-charging in the first phase, and then performs integration operation on the same integration capacitor in the second phase. By using single capacitor integration, the instability of the delay generator existed in the phase-interpolation DDS can be avoided, and the impact caused by capacitance error in the circuit implementation also can be reduced. Furthermore, without ROM tables, the proposed DDS using pre-charging integration not only reduces the spurious level of the clock output, but also has a low hardware complexity.

This paper presents novel phase-continuous frequency hopping (FH) control for a direct frequency synthesizer (DFS) using a quadrature mixer driven by two direct digital synthesizers (DDSs). To achieve wideband FH in both of the lower and the upper sidebands of a local frequency in a quadrature mixer, the proposed DFS decreases or increases the phase of DDS output signals corresponding to frequency offset from a local frequency of the quadrature mixer. To realize phase decrement, the proposed method adds a complement number in a phase accumulator of a DDS, while a conventional DDS does not use phase decrement but uses a switchable combiner. In addition, as the phase accumulator output changes continuously by summing phase increment, the proposed method always assures phase continuity of a DFS output signal, which ends up suppressing sidelobe level of frequency hopped signals. The calculation and measurement results indicate that a sidelobe of a signal spectrum using the proposed phase continuous method is approximately 10 dB better than that using a conventional phase discontinuous method.

This paper presents high-speed low-power small-area accumulator designs to be used in DDFS systems. To reduce the Numerically Controlled Oscillator (NCO) design complexity and size, only the most significant bits of the accumulator drive the phase to amplitude mapping block. Those bits need to be updated on every sampling clock, while the least significant bits of the accumulator are not visible to the rest of the DDFS design and can be updated less frequently, which motivated the development of new accumulator designs. Without performance degradation, the proposed designs relieve constraints in implementation, and hence they can be employed for GHz-range DDFS, reduce power consumption up to 82% compared to standard accumulator design, and minimize chip area. For further power reduction, the proposed designs place the phase modulation adder at the front of the accumulator.