High-Speed Low-Power Small-Area Accumulator Designs for Direct Digital Frequency Synthesizers
Summary :
This paper presents high-speed low-power small-area accumulator designs to be used in DDFS systems. To reduce the Numerically Controlled Oscillator (NCO) design complexity and size, only the most significant bits of the accumulator drive the phase to amplitude mapping block. Those bits need to be updated on every sampling clock, while the least significant bits of the accumulator are not visible to the rest of the DDFS design and can be updated less frequently, which motivated the development of new accumulator designs. Without performance degradation, the proposed designs relieve constraints in implementation, and hence they can be employed for GHz-range DDFS, reduce power consumption up to 82% compared to standard accumulator design, and minimize chip area. For further power reduction, the proposed designs place the phase modulation adder at the front of the accumulator.
- Publication
- IEICE TRANSACTIONS on Fundamentals Vol.E88-A No.5 pp.1373-1378
- Publication Date
- 2005/05/01
- Publicized
- Online ISSN
- DOI
- 10.1093/ietfec/e88-a.5.1373
- Type of Manuscript
- LETTER
- Category
- Circuit Theory
Authors
Keyword
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Edward MERLO, Kwang-Hyun BAEK, "High-Speed Low-Power Small-Area Accumulator Designs for Direct Digital Frequency Synthesizers" in IEICE TRANSACTIONS on Fundamentals,
vol. E88-A, no. 5, pp. 1373-1378, May 2005, doi: 10.1093/ietfec/e88-a.5.1373.
Abstract: This paper presents high-speed low-power small-area accumulator designs to be used in DDFS systems. To reduce the Numerically Controlled Oscillator (NCO) design complexity and size, only the most significant bits of the accumulator drive the phase to amplitude mapping block. Those bits need to be updated on every sampling clock, while the least significant bits of the accumulator are not visible to the rest of the DDFS design and can be updated less frequently, which motivated the development of new accumulator designs. Without performance degradation, the proposed designs relieve constraints in implementation, and hence they can be employed for GHz-range DDFS, reduce power consumption up to 82% compared to standard accumulator design, and minimize chip area. For further power reduction, the proposed designs place the phase modulation adder at the front of the accumulator.
URL: https://global.ieice.org/en_transactions/fundamentals/10.1093/ietfec/e88-a.5.1373/_p
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@ARTICLE{e88-a_5_1373,
author={Edward MERLO, Kwang-Hyun BAEK, },
journal={IEICE TRANSACTIONS on Fundamentals},
title={High-Speed Low-Power Small-Area Accumulator Designs for Direct Digital Frequency Synthesizers},
year={2005},
volume={E88-A},
number={5},
pages={1373-1378},
abstract={This paper presents high-speed low-power small-area accumulator designs to be used in DDFS systems. To reduce the Numerically Controlled Oscillator (NCO) design complexity and size, only the most significant bits of the accumulator drive the phase to amplitude mapping block. Those bits need to be updated on every sampling clock, while the least significant bits of the accumulator are not visible to the rest of the DDFS design and can be updated less frequently, which motivated the development of new accumulator designs. Without performance degradation, the proposed designs relieve constraints in implementation, and hence they can be employed for GHz-range DDFS, reduce power consumption up to 82% compared to standard accumulator design, and minimize chip area. For further power reduction, the proposed designs place the phase modulation adder at the front of the accumulator.},
keywords={},
doi={10.1093/ietfec/e88-a.5.1373},
ISSN={},
month={May},}
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TY - JOUR
TI - High-Speed Low-Power Small-Area Accumulator Designs for Direct Digital Frequency Synthesizers
T2 - IEICE TRANSACTIONS on Fundamentals
SP - 1373
EP - 1378
AU - Edward MERLO
AU - Kwang-Hyun BAEK
PY - 2005
DO - 10.1093/ietfec/e88-a.5.1373
JO - IEICE TRANSACTIONS on Fundamentals
SN -
VL - E88-A
IS - 5
JA - IEICE TRANSACTIONS on Fundamentals
Y1 - May 2005
AB - This paper presents high-speed low-power small-area accumulator designs to be used in DDFS systems. To reduce the Numerically Controlled Oscillator (NCO) design complexity and size, only the most significant bits of the accumulator drive the phase to amplitude mapping block. Those bits need to be updated on every sampling clock, while the least significant bits of the accumulator are not visible to the rest of the DDFS design and can be updated less frequently, which motivated the development of new accumulator designs. Without performance degradation, the proposed designs relieve constraints in implementation, and hence they can be employed for GHz-range DDFS, reduce power consumption up to 82% compared to standard accumulator design, and minimize chip area. For further power reduction, the proposed designs place the phase modulation adder at the front of the accumulator.
ER -
English
