To improve metal oxide semiconductor field effect transistors (MOSFET) performance, flat interface between gate insulator and silicon (Si) should be realized. In this paper, the influence of Si surface roughness on electrical characteristics of MOSFET with hafnium oxynitride (HfON) gate insulator formed by electron cyclotron resonance (ECR) plasma sputtering was investigated for the first time. The surface roughness of Si substrate was reduced by Ar/4.9%H2 annealing utilizing conventional rapid thermal annealing (RTA) system. The obtained root-mean-square (RMS) roughness was 0.07nm (without annealed: 0.18nm). The HfON was formed by 2nm-thick HfN deposition followed by the Ar/O2 plasma oxidation. The electrical properties of HfON gate insulator were improved by reducing Si surface roughness. It was found that the current drivability of fabricated nMOSFETs was remarkably increased by reducing Si surface roughness. Furthermore, the reduction of Si surface roughness also leads to decrease of the 1/f noise.

To improve metal oxide semiconductor field effect transistors (MOSFET) performance, flat interface between gate insulator and silicon should be realized. In this paper, flattening process of Si surface below 1000 utilizing Ar/4.9%H2 annealing and its effect on ultrathin HfON gate insulator formation were investigated. The Si(100) substrates were annealed using conventional rapid thermal annealing (RTA) system in Ar or Ar/4.9%H2 ambient for 1 h. The surface roughness of Ar/4.9%H2-annealed Si was small compared to that of Ar-annealed Si because the surface oxidation was suppressed. The obtained root mean square (RMS) roughness was 0.08 nm (as-cleaned: 0.20 nm) in case of Ar/4.9%H2-annealed at 1000 measured by tapping mode atomic force microscopy (AFM). The HfON surface was also able to be flattened by reduction of Si surface roughness. The electrical properties of HfON gate insulator were improved by the reduction of Si surface roughness. We obtained equivalent oxide thickness (EOT) of 0.79 nm (as-cleaned: 1.04 nm) and leakage current density of 3.510-3 A/cm2 (as-cleaned: 6.110 -1 A/cm2) by reducing the Si surface roughness.

Magnetic tunnel junctions (MTJ), i.e., structures consisting of two ferromagnetic layers (FM1 and FM2), separated by a very thin insulator barrier (I), have recently attracted attention for their large tunneling magnetoresistance (TMR) which appears when the magnetization of the ferromagnets of FM1 and FM2 changes their relative orientation from parallel to antiparallel in an applied magnetic field. Using an ultrahigh vacuum magnetron sputtering system, a variety of MTJ structures have been explored. Double Hc magnetic tunnel junction, NiFe/Al2O3/Co and FeCo/Al2O3/Co, were fabricated directly using placement of successive contact mask. The tunnel barrier was prepared by in situ plasma oxidation of thin Al layers sputter deposited. For NiFe/Al2O3/Co junctions, the maximum TMR value reaches 5.0% at room temperature, the switching field can be less than 10 Oe and the relative step width is about 30 Oe. The junction resistance changes from hundreds of ohms to hundreds of kilo-ohms and TMR values decrease monotonously with the increase of applied junction voltage bias. For FeCo/Al2O3/Co junctions, TMR values exceeding 7% were obtained at room temperature. It is surprising that an inverse TMR of 4% was observed in FeCo/Al2O3/Co. The physics governing the spin polarization of tunneling electrons remains unclear. Structures, NiFe/FeMn/NiFe/Al2O3/NiFe, in which one of the FM layers is exchange biased with an antiferromagnetic FeMn layer, were also prepared by patterning using optical lithography techniques. Thus, the junctions exhibit two well-defined magnetic states in which the FM layers are either parallel or antiparallel to one another. TMR values of 16% at room temperature were obtained. The switching field is less than 10 Oe and step width is larger than 30 Oe.