We propose a new three-dimensional (3D) NAND flash memory array having Tied Bit-line and Ground Select Transistor (TiGer) [1]. Channels are stacked in the vertical direction to increase the memory density without the device size scaling. To distinguish stacked channels, a novel operation scheme is introduced instead of adding supplementary control gates. The stacked layers are selected by using ground select line (GSL) and common source line (CSL). Device structure and fabrication process are described. Operation scheme and simulation results for program inhibition are also discussed.

In performing the program operation of the NAND-type flash memory array, the program-inhibited cell is applied by a positive voltage at the gate, i.e., word-line (WL) on the floating channel while the program cell is applied by program voltage as the two ends, drain select line (DSL) and source select line (SSL), are turned on with grounded bit-line (BL). In this manner, the self-boosting of silicon channel to avoid unwanted program operation is made possible. As the flash memory device is aggressively scaled down and the channel doping concentration is increased accordingly, the coupling phenomena among WL, floating gate (FG)/storage node, and silicon channel, which are crucial factors in the self-boosting scheme, should be investigated more thoroughly. In this work, the dependences of self-boosting of channel potential on channel length and doping concentration in the 2-D conventional planar and 3-D FinFET NAND-type flash memory devices based on bulk-silicon are investigated by both 2-D and 3-D numerical device simulations. Since there hardly exists realistic ways of measuring the channel potential by physical probing, the series of simulation works are believed to offer practical insights in the variation of channel potential inside a flash memory device.