We propose a new three-dimensional (3D) NAND flash memory array having Tied Bit-line and Ground Select Transistor (TiGer) [1]. Channels are stacked in the vertical direction to increase the memory density without the device size scaling. To distinguish stacked channels, a novel operation scheme is introduced instead of adding supplementary control gates. The stacked layers are selected by using ground select line (GSL) and common source line (CSL). Device structure and fabrication process are described. Operation scheme and simulation results for program inhibition are also discussed.
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Se Hwan PARK, Yoon KIM, Wandong KIM, Joo Yun SEO, Hyungjin KIM, Byung-Gook PARK, "Novel Three Dimensional (3D) NAND Flash Memory Array Having Tied Bit-line and Ground Select Transistor (TiGer)" in IEICE TRANSACTIONS on Electronics,
vol. E95-C, no. 5, pp. 837-841, May 2012, doi: 10.1587/transele.E95.C.837.
Abstract: We propose a new three-dimensional (3D) NAND flash memory array having Tied Bit-line and Ground Select Transistor (TiGer) [1]. Channels are stacked in the vertical direction to increase the memory density without the device size scaling. To distinguish stacked channels, a novel operation scheme is introduced instead of adding supplementary control gates. The stacked layers are selected by using ground select line (GSL) and common source line (CSL). Device structure and fabrication process are described. Operation scheme and simulation results for program inhibition are also discussed.
URL: https://global.ieice.org/en_transactions/electronics/10.1587/transele.E95.C.837/_p
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@ARTICLE{e95-c_5_837,
author={Se Hwan PARK, Yoon KIM, Wandong KIM, Joo Yun SEO, Hyungjin KIM, Byung-Gook PARK, },
journal={IEICE TRANSACTIONS on Electronics},
title={Novel Three Dimensional (3D) NAND Flash Memory Array Having Tied Bit-line and Ground Select Transistor (TiGer)},
year={2012},
volume={E95-C},
number={5},
pages={837-841},
abstract={We propose a new three-dimensional (3D) NAND flash memory array having Tied Bit-line and Ground Select Transistor (TiGer) [1]. Channels are stacked in the vertical direction to increase the memory density without the device size scaling. To distinguish stacked channels, a novel operation scheme is introduced instead of adding supplementary control gates. The stacked layers are selected by using ground select line (GSL) and common source line (CSL). Device structure and fabrication process are described. Operation scheme and simulation results for program inhibition are also discussed.},
keywords={},
doi={10.1587/transele.E95.C.837},
ISSN={1745-1353},
month={May},}
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TY - JOUR
TI - Novel Three Dimensional (3D) NAND Flash Memory Array Having Tied Bit-line and Ground Select Transistor (TiGer)
T2 - IEICE TRANSACTIONS on Electronics
SP - 837
EP - 841
AU - Se Hwan PARK
AU - Yoon KIM
AU - Wandong KIM
AU - Joo Yun SEO
AU - Hyungjin KIM
AU - Byung-Gook PARK
PY - 2012
DO - 10.1587/transele.E95.C.837
JO - IEICE TRANSACTIONS on Electronics
SN - 1745-1353
VL - E95-C
IS - 5
JA - IEICE TRANSACTIONS on Electronics
Y1 - May 2012
AB - We propose a new three-dimensional (3D) NAND flash memory array having Tied Bit-line and Ground Select Transistor (TiGer) [1]. Channels are stacked in the vertical direction to increase the memory density without the device size scaling. To distinguish stacked channels, a novel operation scheme is introduced instead of adding supplementary control gates. The stacked layers are selected by using ground select line (GSL) and common source line (CSL). Device structure and fabrication process are described. Operation scheme and simulation results for program inhibition are also discussed.
ER -