We recently determined the values of intrinsic spin-orbit (SO) parameters for In_0.52Al_0.48As/In_0.53Ga_0.47As(10 nm)/In_0.52Al_0.48As (InGaAs/InAlAs) quantum wells (QW), lattice-matched to (001) InP, from the weak localization/antilocalization analysis of the low-temperature magneto-conductivity measurements [1]. We have then studied the subband energy spectra for the InGaAs/InAlAs double QW system from beatings in the Shubnikov de Haas (SdH) oscillations. The basic properties obtained here for the double QW system provides useful information for realizing nonmagnetic spin-filter devices based on the spin-orbit interaction [2].

Chemical sensors are one of the oldest fields of research closely related to the semiconductor technology. From the Ion-Sensitive Field-Effect Transistors (ISFET) in the 70's, through Micro-Electro-Mechanical-System (MEMS) sensors from the end of the 80's, chemical sensors are combining in the 90's MEMS technology with LSI intelligence to devise more selective, sensitive and autonomous devices to analyse complex mixtures. A brief history of chemical sensors from the ISFET to the nowadays LSI integrated sensors is first detailed. Then the states-of-the-art of LSI integrated chemical sensors and their wide range of applications are discussed. Finally the authors propose a brand-new usage of integrated wireless MEMS sensors for remote surveillance of chemical substances, such as food-industry or pharmaceutical products, that are stored in closed environment like a bottle, for a long period. In such environment, in-situ analyse is necessary, and electrical cables, for energy supply or data transfer, cannot be used. Thanks to integrated MEMS, an autonomous long-term in-situ quality deterioration tracking system is possible.

In this work, the effect of device dimension variation and metal wiring scheme on the RF performance of MOSFETs based on 0.13-µm RFCMOS technology has been investigated. Two sets of experiments have been carried out. In the first experiment, two types of source metal wiring options, each with various gate poly pitches, have been investigated. The results showed that the extrinsic capacitances (C^e_gs, C^e_gd) and parasitic resistances tend to increase with increasing gate poly pitch. Both cutoff frequency (f_T) and maximum oscillation frequency (f_max) showed substantial degradation for the larger gate poly pitches. Based on measurement, we propose a simplified model for extrinsic parasitic capacitance as a function of gate poly pitch with different source metal wiring schemes. For the second experiment, the impact of gate metal wiring scheme and the number of gate fingers N_f on the RF performance of MOSFET has been studied. Two different types of gate metal wiring schemes, one with poly layer and the other with M2 layer, are compared. The measurement showed that the capacitance is slightly increased, while gate resistance significantly reduced, with the M2 gate wiring. As a result, f_T is slightly degraded but f_max is significantly improved, especially for larger N_f, with the M2 gate wiring. The results in this work provide useful information regarding device dimension and metal wiring scheme for various RF applications of RF CMOS technology.

In this paper, a Schmitt Trigger based 10T SRAM (ST 10T SRAM) cell with the vertical MOSFET is proposed for low supply voltage operation, and its impacts on cell size, stability and speed performance are investigated. The proposed ST 10T SRAM cell with the vertical MOSFET achieves smaller cell size than the ST 10T SRAM cell with the conventional planar MOSFET. Moreover, the proposed SRAM cell realizes large and constant static noise margin (SNM) against bottom node resistance of the vertical MOSFET without any architectural changes from the present 6T SRAM architecture. The proposed SRAM cell also suppresses the degradation of the read time of the ST 10T SRAM cell due to the back-bias effect free characteristic of the vertical MOSFET. The proposed ST 10T SRAM cell with the vertical MOSFET is a superior SRAM cell for low supply voltage operation with a small cell size, stable operation, and fast speed performance with the present 6T SRAM architecture.

In the current study, stress-induced capacitance determined by direct measurement on MOSFETs was compared with that determined by indirect simulation through the delay of CMOS ring oscillators (ROs) fabricated side by side with MOSFETs. External compressive stresses were applied on <110> silicon-on-insulator (SOI) n-/p-MOSFETs with the ROs in a longitudinal configuration. The measured gate capacitance decreased as the compressive stress on SOI increased, which agrees with the result of the capacitance difference between measured and simulated delay of the ROs. The oscillation frequency shift of the ROs should mainly be attributed to oxide capacitance, aside from the change in mobility of the n-/p-MOSFETs. The result suggests that the stress-induced gate capacitance of partially depleted MOSFETs is an important factor for the capacitance shift in a circuit and that ROs can be used in a vehicle to determine mechanical stress-induced gate capacitance in MOSFETs.

In this paper, Source/Drain (S/D) engineering for high performance (HP) Vertical MOSFET (V-MOSFET) in 3Xnm generation and its beyond is investigated, by using gradual S/D profile while degradation of driving current (I_ON) due to the parasitic series resistance (R_para) is minimized through two-dimensional device simulation taking into account for gate-induced-drain-leakage (GIDL). In general, it is significant to reduce spreading resistance in the case of conventional Planar MOSFET. Therefore, in this study, we focused and analyzed the abruptness of diffusion layer that is still importance parameter in V-MOSFET. First, for improving the basic device performance such as subthreshold swing (SS), I_ON, and R_para, S/D engineering is investigated. The dependency of device performance on S/D abruptness (σ_S/D) for various Lightly Doped Drain Extension (LDD) abruptness (σ_LDD) is analyzed. In this study, Spacer Length (L_SP) is defined as a function of σ_S/D. As σ_S/D becomes smaller and S/D becomes more abrupt, L_SP becomes shorter. SS depends on the σ_S/D rather than the σ_LDD. I_ON has the peak value of 1750 µA/µm at σ_S/D = 2 nm/dec. and σ_LDD=3 nm/dec. when the silicon pillar diameter (D) is 30 nm and the gate length (Lg) is 60 nm. As σ_S/D becomes small, higher I_ON is obtained due to reduction of R_para while SS is degraded. However, when σ_S/D becomes too small in the short channel devices (Lg = 60 nm and Lg = 45 nm), I_ON is degraded because the leakage current due to GIDL is increased and reaches I_OFF limit of 100 nA/µm. In addition, as σ_LDD becomes larger, larger I_ON is obtained in the case of Lg = 100 nm and Lg = 60 nm because channel length becomes shorter. On the other hand, in the case of Lg = 45 nm, as σ_LDD becomes larger, I_ON is degraded because short channel effect (SCE) becomes significant. Next, the dependency of the basic device performance on D is investigated. By slimming D from 30 nm to 10 nm, while SS is improved and approaches the ideal value of 60 mV/Decade, I_ON is degraded due to increase of on-resistance (R_on). From these results, it is necessary to reduce R_para while I_OFF meets limit of 100 nA/µm for designing S/D of HP V-MOSFET. Especially for the V-MOSFET in the 1Xnm generation and its beyond, the influence of the R_para and GIDL on I_ON becomes more significant, and therefore, the trade-off between σ_S/D and I_ON has a much greater impact on S/D engineering of V-MOSFET.

Electrical performances of gate-all-around (GAA) tunneling field-effect transistors (TFETs) based on a silicon germanium (Si_1-xGe_x) layer have been investigated in terms of subthreshold swing (SS), on/off current ratio, on-state current (I_on). Cut-off frequency (f_T) and maximum oscillation frequency (f_max) were demonstrated from small-signal parameters such as effective gate resistance (R_g), gate-drain capacitance (C_gd), and transconductance (g_m). According to the technology computer-aided design (TCAD) simulation results, the current drivability, f_T, and f_max of GAA TFETs based on Si_1-xGe_x layer were higher than those of GAA TFETs based on silicon. The simulated devices had 60 nm channel length and 10 nm channel radius. A GAA TFET with x = 0.4 had maximum I_on of 51.4 µA/µm, maximum f_T of 72 GHz, and maximum f_max of 610 GHz. Additionally, improvements of performance at the presented device with PNPN junctions were demonstrated in terms of I_on, SS, f_T, and f_max. When the device was designed with x = 0.4 and n⁺ layer width (W_n) = 6 nm, it shows I_on of 271 µA/µm, f_T of 245 GHz, and f_max of 1.49 THz at an operating bias (V_GS = V_DS = 1.0 V).

Although the Tunnel Field-Effect Transistor (TFET) is a promising device for ultra-low power CMOS technology due to the ability to reduce power supply voltage and very small off-current, there have been few reports on the control of V_T for TFETs. Unfortunately, the TFET needs a different technique to adjust V_T than the MOSFET by channel doping because most of TFETs are fabricated on SOI substrates. In this paper, we propose a technique to control V_T of the TFET by putting an additional V_T-control doping region (VDR) between source and channel. We examine how much V_T is changed by doping concentration of VDR. The change of doping concentration modulates V_T because it changes the semiconductor work function difference, ψ_s,channel-ψ_s,source, at off-state. Also, the effect of the size of VDR is investigated. The region can be confined to the silicon surface because most of tunneling occurs at the surface. At the same time, we study the optimum width of this region while considering the mobility degradation by doping. Finally, the effect of the SOI thickness on the VDR adjusted V_T of TFET is also investigated.

As an add-on device option for the ultra-low power CMOS technology, the double-gated vertical-channel Tunnel Field-Effect Transistors (TFETs) of different source configurations are comparatively studied from the perspectives of fabrication and current drivability. While the top-source design where the source of the device is placed on the top of the fin makes the fabrication and source engineering much easier, it is more susceptible to parasitic resistance issue. The bottom-source design is difficult to engineer the tunneling barrier and may require a special replacement technique. Examples of the schemes to engineer the tunneling barrier for the bottom-source TFET are suggested. A TCAD simulation study on the bottom-source devices shows that both the parasitic resistance of source region and the current enhancement mechanism by field coupling need be carefully considered in designing the source.

In this paper, we fabricated a gate-all-around bandgap-engineered (BE) silicon-oxide-nitride-oxide-silicon (SONOS) and silicon-oxide-high-k-oxide-silicon (SOHOS) flash memory device with a vertical silicon pillar type structure for a potential solution to scaling down. Silicon nitride (Si₃N₄) and hafnium oxide (HfO₂) were used as trapping layers in the SONOS and SOHOS devices, respectively. The BE-SOHOS device has better electrical characteristics such as a lower threshold voltage (V_TH) of 0.16 V, a higher g_m.max of 0.593 µA/V and on/off current ratio of 5.7610⁸, than the BE-SONOS device. The memory characteristics of the BE-SONOS device, such as program/erase speed (P/E speed), endurance, and data retention, were compared with those of the BE-SOHOS device. The measured data show that the BE-SONOS device has good memory characteristics, such as program speed and data retention. Compared with the BE-SONOS device, the erase speed is enhanced about five times in BE-SOHOS, while the program speed and data retention characteristic are slightly worse, which can be explained via the many interface traps between the trapping layer and the tunneling oxide.

We propose a new three-dimensional (3D) NAND flash memory array having Tied Bit-line and Ground Select Transistor (TiGer) [1]. Channels are stacked in the vertical direction to increase the memory density without the device size scaling. To distinguish stacked channels, a novel operation scheme is introduced instead of adding supplementary control gates. The stacked layers are selected by using ground select line (GSL) and common source line (CSL). Device structure and fabrication process are described. Operation scheme and simulation results for program inhibition are also discussed.

Effects of conductive defects on unipolar resistive random access memory (RRAM) are investigated in order to reduce the operation current for high density and low power RRAM applications. It is clarified that forming voltage decreases with increasing charged conductive defects which are a source of conductive filament (CF) path and with decreasing cell thickness. Random circuit breaker (RCB) network simulation model which is a dynamic percolation simulation model is used to elucidate these effects. From this simulation results, the optimal cell thickness with sufficient conductive defect shows improved resistive switching characteristics such as low forming voltage, small set voltage distribution and low reset current. From the deep understanding of relationship between conductive defect in various cell thickness and other resistive switching parameters, RRAM with low forming voltage and reset current can be obtained and it will be one of the most promising next generation nonvolatile memories.

The performances of the conventional planar type 1T DRAM and the Vertical type 1T DRAM are compared based on structure difference using a fully-consistent device simulator. We discuss the structural advantage of the Vertical type 1T-DRAM in comparison with the conventional planar type 1T-DRAM, and evaluate their performance in each operating mode such as write, erase, read, and hold; and discuss its cell performances such as Cell Current Margin and data retention. These results provide a useful guideline designing the high performance Vertical type 1T-DRAM cell.

In this paper, we propose a new low power nonvolatile counter unit based on Magnetic Tunnel Junction (MTJ) with fine-grained power gating. The proposed counter unit consists of only a single latch with two MTJs. We verify the basic operation and estimate the power consumption of the proposed counter unit. The operating power consumption of the proposed nonvolatile counter unit is smaller than the conventional one below 140 kHz. The power of the proposed unit is 74.6% smaller than the conventional one at low frequency.

In this paper, a 60 nm-thick ferroelectric film of poly(vinylidene fluoride–trifluoroethylene) on a flexible substrate of aluminum foil was fabricated and characterized. Compared to pristine silicon wafer, Al-foil has very large root-mean-square (RMS) roughness, thus presenting challenges for the fabrication of flat and uniform electronic devices on such a rough substrate. In particular, RMS roughness affects the leakage current of dielectrics, the uniformity of devices, and the switching time in ferroelectrics. To avoid these kinds of problems, a new thin film fabrication method adopting a detach-and-transfer technique has been developed. Here, 'detach' means that the ferroelectric film is detached from a flat substrate (sacrificial substrate), and 'transfer' refers to the process of the detached film being moved onto the rough substrate (main substrate). To characterize the dielectric property of the transferred film, polarization and voltage relationships were measured, and the results showed that a hysteresis loop could be obtained with low leakage current.

We developed a flexible-logic-gate single-electron device (SED) in which logic functions can be selected by changing the voltage applied to the control gate. It consists of an array of nanodots with multiple inputs and multiple outputs. Since the gate electrodes couple capacitively to the many dots underneath, complicated characteristics depending on the combination of the gate voltages yield a selectable logic gate when some of the gate electrodes are used as control gates. One of the important issues is how to design the arrangement of nanodots and gate electrodes. In this study, we fabricated a Si nanodot array with two simple input gates and two output terminals, in which each gate was coupled to half of the nanodot array. Even though the device had a very simple input-gate arrangement and just one control gate, we could create a half-adder function through the use of current maps as functions of the input gate voltages. We found that the nanodots evenly coupled capacitively to both input gates played an important role in getting a basic set of logic functions. Moreover, these results guarantee that a more complicated input-gate structure, in which each gate evenly couples many nanodots, will yield more complicated functions.

In this paper, we analyze current-voltage characteristics of InSb/AlInSb triple-barrier resonant tunneling diodes (TBRTDs) with spin-splitting under zero magnetic fields. The InSb has very small effective mass, thus we can obtain large spin-splitting by Rashba spin-orbit interaction due to asymmetric InSb/AlInSb quantum wells. In our model, broadening of each resonant tunneling level and spin-splitting energy can be considered to calculate spin-polarized resonant tunneling current.

We have studied resistance-switching properties of RF sputtered Si-rich oxides sandwiching with Pt electrodes. By sweeping bias to the top Pt electrode, non-polar type resistance switching was observed after a forming process. In comparison to RF sputtered TiO_x case, significant small current levels were obtained in both the high resistance state (HRS) and the low resistance state (LRS). And, even with decreasing SiO_x thickness down to 8 nm from 40 nm, the ON/OFF ratio in resistance-switching between HRS and LRS as large as 10³ was maintained. From the analysis of current-voltage characteristics for Pt/SiO_x on p-type Si(100) and n-type Si(100), it is suggested that the red-ox (REDction and OXidation) reaction induced by electron fluence near the Pt/SiO_x interface is of importance for obtaining the resistance-switching behavior.

Pentacene-based organic field-effect transistors (OFETs) with SiO₂ and HfON gate insulators have been fabricated, and the effect of gate insulator on the electrical properties of pentacene-based OFETs and the microstructures of pentacene films were investigated. It was found that the grain size for pentacene film deposited on HfON gate insulator is larger than that for pentacene film deposited on SiO₂ gate insulator. Due to the larger grain size, pentacene-based OFET with HfON gate insulator shows better electrical properties compared to pentacene-based OFET with SiO₂ gate insulator. Meanwhile, low-temperature (such as 140) fabricated pentacene-based OFET with HfON gate insulator was also investigated. The OFET fabricated at 140 shows a small subthreshold swing of 0.14 V/decade, a large on/off current ratio of 4 10⁴, a threshold voltage of -0.65 V, and a hole mobility of 0.33 cm²/Vs at an operating voltage of -2 V.

Recently, the 3-D vertical Floating Gate (FG) type NAND cell arrays with the Sidewall Control Gate (SCG), such as ESCG, DC-SF and S-SCG, are receiving attention to overcome the reliability issues of Charge Trap (CT) type device. Using this novel cell structure, highly reliable flash cell operations were successfully implemented without interference effect on the FG type cell. However, the 3-D vertical FG type cell has large cell size by about 60% for the cylindrical FG structure. In this point of view, we intensively investigate the scalability of the FG width of the 3-D vertical FG NAND cells. In case of the planar FG type NAND cell, the FG height cannot be scaled down due to the necessity of obtaining sufficient coupling ratio and high program speed. In contrast, for the 3-D vertical FG NAND with SCG, the FG is formed cylindrically, which is fully covered with surrounded CG, and very high CG coupling ratio can be achieved. As results, the scaling of FG width of the 3-D vertical FG NAND cell with S-SCG can be successfully demonstrated at 10 nm regime, which is almost the same as the CT layer of recent BE-SONOS NAND.

In this paper, we designed and fabricated large scale micro-light-emitting-diode (LED) arrays and silicon driver for single chip device for realizing as prototypes of heterogeneous optoelectronic integrated circuits (OEICs). The large scale micro-LED arrays were separated by a dry etching method from mesa structure to 16,384 pixels of 128 128, each with a size of 15 µm in radius. Silicon driver was designed the additional bonding pad on each driving transistor for bonding with micro-LED arrays. Fabricated micro-LED arrays and driver were flip-chip bonded using anisotropic conductive adhesive.

In this paper, we report a reduction in the access resistance of InP/InGaAs composite-channel metal-oxide-semiconductor field-effect-transistors (MOSFETs) with a back-source electrode. The source region has two electrodes. The source electrode on the surface side is connected to the channel through a doped layer and supplies the electrons. The back-source electrode is constructed under the channel layer and is insulated from the doped layer in order to avoid current leakage. The function of the back-source electrode is to increase the carrier concentration in the channel layer of the source region. In the simulation, the electron density in the channel layer is almost doubled by the effect of the back-source voltage. The fabricated III-V MOSFET has a channel length of 6 µm. A 6% increase in the maximum drain current density (I_d) and a 6.8% increase in the transconductance (g_m) (V_d = 2 V) are observed. The increase in the carrier density in the channel is estimated to be 20% when the applied voltage of the back-source electrode is 6 V.

We have investigated the low-power circuit applicability of hetero-gate-dielectric tunneling field-effect transistors (HG TFETs). Based on the device-level comparison of HG, SiO₂-only and high-k-only TFETs, their circuit performance and energy consumption have been discussed. It has been shown that HG TFETs can deliver 14400x higher performance than the SiO₂-only TFETs and 17x higher performance than the high-k-only TFETs due to its higher on current and lower capacitance at the same static power, same power supply. It has been revealed that HG TFETs have better voltage scalability than the others. It is because HG TFETs dissipate only 8% of energy consumption of SiO₂-only TFETs and 17% of that of high-k-only TFETs under the same performance condition.

The fringe field effects of nano-electromechanical (NEM) nonvolatile memory cells have been investigated analytically for the accurate evaluation of NEM memory cells. As the beam width is scaled down, fringe field effect becomes more severe. It has been observed that pull-in, release and hysteresis voltage decrease more than our prediction. Also, the fringe field on cell characteristics has been discussed.

In this paper, we report the reduction in the base-collector capacitance (C_BC) of InP/InGaAs double heterojunction bipolar transistors with buried SiO₂ wires (BG-HBT). In a previous trial, we could not confirm a clear difference between the C_BC of the conventional HBT and that of the BG-HBT because the subcollector layer was thicker than expected. In this study, the interface between the collector and the subcollector was shifted to the middle of the SiO₂ wires by adjusting the growth temperature, and a reduction in C_BC with buried SiO₂ wires was confirmed. The estimated C_BC of the BG-HBT was 7.6 fF, while that of the conventional HBT was 8.6 fF. This 12% reduction was in agreement with the 10% reduction calculated according to the designed size.

A low-power switching method using a bootstrapping circuit is proposed for a high-speed output driver of transmitter. Compared with a conventional output driver, the proposed scheme employs only nMOSFETs to transmit data. The bootstrapping circuit ensures the proper switching of nMOSFET. The proposed scheme is simulated and fabricated using a 0.18 µm CMOS technology, showing 10.2% lower power consumption than a conventional switching driver at 2.5 Gb/s data rate.

We herein investigate the operation stability of the single-electron-pump (SEP) refrigerator with respect to thermal and dimensional fluctuations. The SEP refrigerator was found to successfully demonstrate single-electron extraction and injection at temperatures up to 2 K. Although the dimensional fluctuation in junction capacitance will seriously affect operation, the effect of the gate capacitance fluctuation is unlikely to be severe.

Radiation integral areas are localized and reduced based upon the locality of scattering phenomena. In the high frequency, the scattering field is given by the currents, not the entire region, but on the local areas near the scattering centers, such as the stationary phase points and edge diffraction points, due to the cancelling effect of integrand in the radiation integral. The numerical calculation which this locality is implemented into has been proposed for 2-dimensional problems. The scattering field can be approximated by integrating the currents weighted by the adequate function in the local areas whose size and position are determined appropriately. Fresnel zone was previously introduced as the good criterion to determine the local areas, but the determination method was slightly different, depending on the type of scattering centers. The objective of this paper is to advance the Fresnel zone criteria in a 2-dimensional case to the next stage with enhanced generality and applicability. The Fresnel zone number is applied not directly to the actual surface but to the virtual one associated with the modified surface-normal vector satisfying the reflection law. At the same time, the argument in the weighting function is newly defined by the Fresnel zone number instead of the actual distance from the scattering centers. These two revisions bring about the following three advantages; the uniform treatment of various types scattering centers, the smallest area in the localization and applicability to 3-dimensional problems.

Thin-film 2-arm Archimedean spiral antenna coupled with a bismuth (Bi) microbolometer was fabricated on a fused quartz substrate backed by cupper (Cu) plate reflector. Antenna patterns of the device agreed with the theoretical patterns derived from the imaging force model at 100 GHz band. The detected voltages of the antenna exhibited a periodic variation with changing the thickness of the substrate. The maximum and minimum detected voltages were obtained when the substrate thickness was odd and even integer multiples of a quarter of the wavelength in the substrate, respectively. Furthermore, the detected voltages were almost constant within the change of 3 dB ranging from 76.9 to 106.8 GHz. The wide band characteristic of the antenna was obtained.

This paper presents the evaluation of the L-2L de-embedding method with misalignment of the contact position. The issues of misalignment of the contact position are investigated. The analysis of misalignment in the L-2L de-embedding procedure is performed. Two comparisons are carried out to verify the error of the L-2L de-embedding method. The calculation percent error in quality factor of the transmission line becomes up to 9.0%, while the transistor S-parameter error percentage becomes up to 21% at 60 GHz in the experimental results. The results show that the measurement errors, caused by the misalignment of the contact position, should be considered carefully.

This paper proposes a new biquad structure based on a flipped voltage follower (FVF) for low-power and wide-bandwidth (BW) low pass filter. The proposed biquad structure consists of an FVF and a source follower (SF) for complex pole pair generation and zero cancellation. The presented design provides good linearity at low power consumption, owing to the voltage follower structures. A power/BW ratio (PBWR) is suggested as a performance metric to compare power efficiency to bandwidth, and the proposed biquad structure shows excellent PBWR, especially for low quality factor (Q) design. As a prototype, a fourth order Bessel filter was fabricated in 0.18 µm CMOS technology. The measured BW, power consumption, IIP3, and FoM are 120 MHz, 180 µW, 15 dBm, and 0.34 fJ, respectively.

In order to improve the address discharge characteristics, we propose the modified selective reset waveform utilizing the address-bias voltage (V_a-bias) during the ramp-up period. It is revealed that the proper V_a-bias makes the weak discharge between the address and scan electrodes which plays a role in sufficiently removing the wall charge, thereby contributing to minimizing the wall-voltage variation during the address-period. As a result of adopting the V_a-bias in the conventional selective reset driving waveform, it was found that the address discharge delay time can be shortened by approximately 40 ns and the address period of each subfield can be significantly reduced by about 43 µs.

A design of dual band amplifier using composite right/left handed (CRLH) transmission line structure is described. First, two single-band matching networks are designed for two frequencies, and they are synthesized into one dual band matching network. It is shown that CRLH transmission lines with arbitrary dual frequencies and dual electrical lengths can be designed. The CRLH transmission line section for the dual band matching network is implemented by lumped inductors and capacitors as the left handed (LH) section, and normal transmission line elements as the right handed (RH) section. As an example, a dual band amplifier for 1800 MHz and 2300 MHz is designed and measured. The simulated and measured performances well verify the proposed design by showing good matching and gain responses at the desired frequencies.

A sub-mW current-reuse CMOS VCO is presented for wireless sensor network applications. In order to break the interdependence between the current consumption and the phase noise performance in the conventional current-reuse structure, a tail current source is added to the switching core in such a way that they are simultaneously switched during operation. With this, the current consumption can be maintained at a minimum level while the FET size can be optimally determined for large swing and good phase noise performances. The proposed VCO's advantage of achieving low phase noise at low current consumption is clearly demonstrated by simulations in comparison to the conventional structure. The proposed VCO is implemented in 0.13 µm CMOS. It dissipates 0.6 mW from 1.2 V supply. The measured phase noise at the output frequency of 2.28 GHz is -121 dBc/Hz at 1 MHz offset.

In this paper, a fifth order curer low-pass filter using as switched-capacitor (SC) architecture is proposed and fabricated with TSMC 0.18 µm CMOS process. A fully differential SC is adopted via the bilinear transform of the corresponding analogue RLC passive prototype. To reach the largest possible input dynamic range and save chip area, the method of dynamic range scaling and minimum capacitor scaling is used. Measured results show that the proposed filter achieves a pass-band of 12.1 MHz with a sampling rate of 100 MHz, a SFDR of 50 dB, a stop-band attenuation greater than 50 dB and a power consumption of 48.5 mW at 1.8 V power supply. Including pads, the chip area occupies 1.515 (1.391.09) mm². This paper has the feature of low noise, excellent linearity of the filter, and high stability. The experimental results show that it has perfect performance for WiMAX applications and standard is recommended.