A multiband T-shaped monopole antenna for WLAN/WiMAX applications is presented. The T-shaped monopole is comprised of two horizontal arms of different lengths, which generate two separate resonant modes for 2.5/5.5 GHz WLAN/WiMAX bands, and with a shortened parasitic element, which generates a middle resonant mode for 3.5 GHz WiMAX band, for seamless wireless network access applications. The proposed antenna has been successfully simulated and implemented. Both results of simulation and measurement show good agreement. For the lower band from 2.3 to 2.7 GHz, the gain varies in the range of 2.5-3.3 dB, while the radiation efficiency is from 72% to 85% over the band. As for the middle band from 3.3 to 3.7 GHz, the gain varies from 1.5 to 2.0 dB, and the radiation efficiency is from 62% to 70%. As for the upper band from 5.2 to 5.8 GHz, the antenna gain varies from 5.4 to 5.9 dB, and the radiation efficiency is from 63% to 66%.

A 5.6-GHz 1-V balanced LC-tank Colpitts voltage controlled oscillator is designed and implemented with a TSMC 0.18-µm CMOS process. This proposed Colpitts VCO circuit adopts two single-ended complementary LC-tank VCOs coupled by two pairs of varactors. The proposed VCO operates at low power consumption because it has the same dc current path as the np-MOSFETs. The Measured results of the proposed VCO achieve tuning range of 670 MHz from 5.23 to 5.9 GHz while the controlled voltage is tuned from 0 to 1-V, phase noise of -118.8 dBc/Hz at 1 MHz offset frequency from the carrier of 5.6 GHz and output power of -10.97 dBm at the supply voltage of 1 V. The power consumption of the core circuit is 1.79 mW and the chip area including pads is 0.451 (0.55 0.82) mm2.

A novel divide-by-3 injection-locked frequency divider (ILFD) is proposed. The ILFD circuit is realized with a cross-coupled n-core MOS LC-tank oscillator embedded with a push-push signal generator and two injection MOSFETs for coupling the injection signal into the resonator. The ILFD uses the linear mixer to extend the locking range and has been implemented in a standard 0.18 µm CMOS process. The core power consumption of the ILFD core is 3.12 mW. The divider's free-running frequency is tunable from 4.26 GHz to 4.9 GHz by tuning the varactor's control bias, and at the incident power of 0 dBm the locking range of the ILFD used as a divide-by-3 divider is 1.5 GHz, from 12.5 GHz to 14.0 GHz.

This paper presents a computer-aided design procedure of simulated annealing algorithm to optimize dual-wideband microstrip line filters with symmetrical at least 500 MHz bandwidths respectively. This method demonstrates the superiority of designing microstrip line dual-band filters. The value of characteristic impedances and electrical lengths of transmission lines synthesizing 2.4 GHz and 5.2 GHz dualband filters with a single input and a single output are adjusted to the annealing process by the optimization algorithm. The fabricated dual-wideband spectral transmittance and reflectance curves of these filters applying this method all effectively achieved desired high performances and resulted in a lower cost dual-band filters and open the way to commercial mass production. The method is applicable not only in 2.4 GHz and 5.2 GHz, but can be applied to any other multi-frequency bands.

This letter presents a new quadrature voltage-controlled oscillator (QVCO) consisting of two n-core Colpitts voltage-controlled oscillators (VCOs) with a tail inductor. The VCOs are used as a single-ended injected injection-locked frequency divider (ILFD). The output of the tail inductor in one ILFD is injected into the injection node in the other ILFD and vice versa. The proposed QVCO has been implemented in the 0.18 µm CMOS technology. At the supply voltage of 1.0 V, the power consumption is 1.8 mW. The free-running frequency is tunable from 4.68 GHz to 5.03 GHz as the tuning voltage is varied from 0.0 V to 1.8 V. The measured phase noise is -113.58 dBc/Hz at the 1 MHz frequency offset from the oscillation frequency of 5.03 GHz and the figure of merit (FOM) of the QVCO is -185.06 dBc/Hz.

This paper proposes a wide-locking range divide-by-3 injection-locked frequency divider (ILFD) fabricated in the 90 nm 1P9M CMOS technology. The divider consists of an nMOS cross-coupled LC oscillator and two injection MOSFETs in series with the cross-coupled nMOSFETs. The ILFD is formed with two linear mixers which share the same dc current so that a low power ILFD can be designed. At the supply voltage of 0.7 V, the free-running frequency is from 10.18 to 11.56 GHz, the current and power consumption of the divider without buffers are 2.8 mA and 1.96 mW, respectively. At the incident power of 0 dBm, the total operational locking range is 4.94 GHz, from the incident frequency 29.96 to 34.9 GHz.

A 6–10-GHz broadband low noise amplifier (LNA) and transmitting amplifier (TA) for direct sequence ultra-wideband (DS-UWB) are presented. The LNA and TA are fabricated with the 0.18-µm 1P6M standard CMOS process. The CMOS LNA and TA are checked by on-wafer measurement with the DC supply voltage of 1.5 V. From 6–10 GHz, the broadband LNA exhibits a noise figure of 5.3–6.2 dB, a gain of 11–13.8 dB, a P1 dB of -15.7 - -10.8 dBm, a IIP3 of -5.5 - -1 dBm, a DC power consumption of 12 mW, and an input/output return loss higher than 11/12 dB, respectively. From 6–10 GHz, the broadband TA exhibits a gain of 7.6–10.5 dB, a OP1 dB of 2.8–6.1 dBm, a OIP3 of 12.3–15.1 dBm, and a PAE of 8.8–17.6% @ OP1 dB, and a η of 9.7–21.1% @ OP1 dB, and an input/output return loss higher than 6.8/3.2 dB, respectively.

In this paper, we propose a heuristic multicast routing algorithm, which minimizes the cost while satisfying both the wavelength required and hop length selection. The algorithm consists of two subproblems: the wavelength assignment & the routing path selection. For solving the wavelength assignment subproblem, an auxiliary graph is created where by the nodes and the links in the original network are transformed to the edges and the vertices, respectively, and the same availability wavelength of each edge is taken into a multicast group. Furthermore, for solving the routing path selection subproblem, the shortest-path routing strategy is adopted to choose transmission path between two multicast groups. Simulation results show that our algorithm performs much better than previously proposed algorithms with increasing call-connection probability by 28% and reducing the blocking probability by 52%.

This paper presents a novel method of designing microstrip line multi-frequencies band filters by applying the SIR (stepped impedance resonators) technology. Utilizing the S-parameter and the ABCD parameters of a two-port network is for the analysis of short-circuited and open-circuited resonators with various combinations of series and shunt sequences. By controlling the impedance ratio of the resonators, both center frequencies of the two passbands then are determined. Moreover, a global synthesis approach is also discussed on miniaturization. A simplified architecture based on bent SIR offers the 50% area reduction of layout. Technology of matching circuit creates higher performance multi-band filter. We adjust impedance and electrical length of transmission line (TL) to compensate multi-band and bending for matches and highly improve the insertion and reflection loss. Simulation and measurement are performed to validate our method and are pretty matched.

Novel low phase noise quadrature voltage-controlled oscillator (QVCO) and quadrature injection locked frequency divider (QILFD) with two coupled Hartley VCOs are proposed and implemented using the standard TSMC 0.18 µm CMOS 1P6M process. The QVCO employs pMOS as the core to reduce the up-conversion of low-frequency device noise to RF phase noise. It uses super-harmonic coupling technique to couple two differential Hartley VCOs and four small-size coupling transistors to set the directivity of quadrature output phases. At the 1.7 V supply voltage, the output phase noise of the QVCO is -124 dBc/Hz at 1 MHz offset frequency from the carrier frequency of 4.12 GHz, and the figure of merit is -185 dBc/Hz. At the supply voltage of 1.7 V, the total power consumption is 13.1 mW. At the supply voltage of 1.5 V, the tuning range of the free-running QILFD is from 2.05 GHz to 2.36 GHz, about 310 MHz, and the locking range of the ILFD is from 3.99 to 5.19 GHz, about 1.20 GHz, at the injection signal power of 0 dBm.

In this paper, a fifth order curer low-pass filter using as switched-capacitor (SC) architecture is proposed and fabricated with TSMC 0.18 µm CMOS process. A fully differential SC is adopted via the bilinear transform of the corresponding analogue RLC passive prototype. To reach the largest possible input dynamic range and save chip area, the method of dynamic range scaling and minimum capacitor scaling is used. Measured results show that the proposed filter achieves a pass-band of 12.1 MHz with a sampling rate of 100 MHz, a SFDR of 50 dB, a stop-band attenuation greater than 50 dB and a power consumption of 48.5 mW at 1.8 V power supply. Including pads, the chip area occupies 1.515 (1.391.09) mm2. This paper has the feature of low noise, excellent linearity of the filter, and high stability. The experimental results show that it has perfect performance for WiMAX applications and standard is recommended.

This paper proposes a wide-locking range divide-by-3 frequency divider employing 3D helical inductors fabricated in the 0.18-µm 1P6M CMOS technology. The divider consists of an nMOS cross-coupled LC oscillator and two injection MOSFETs in series with the cross-coupled NMOSFETs, and the LC resonator is composed of two 3D helical inductors and varactors. The aim of using 3D inductor is to reduce chip size. At the supply voltage of 1.2 V, the divider free-running frequency is tunable from 2.1 GHz to 2.6 GHz, and at the incident power of 0 dBm the locking range is about 2.11 GHz (29.16%), from the incident frequency 5.99 GHz to 8.1 GHz. The core power consumption is 4.56 mW. The die area is 0.6640.831 mm2.

This paper presents a quadrature injection locked frequency divider (ILFD) employing tunable active inductors (TAIs), which are used is to extend the locking range and to reduce die area. The CMOS ILFD is based on a new quadrature voltage-controlled oscillator (VCO) with cross-coupled switching pairs and TAI-C tanks, and was fabricated in the 0.18-µm 1P6M CMOS technology. The divide-by-2 LC-tank ILFD is performed by adding injection MOSFETs between the differential outputs of the VCO. Measurement results show that at the supply voltage of 1.8 V, the divider free-running frequency is tunable from 1.34 GHz to 3.07 GHz, and at the incident power of 0 dBm the locking range is about 6 GHz (137%), from the incident frequency 1.37 GHz to 7.38 GHz. The core power consumption is 22.8 mW. The die area is 0.630.55 mm2.

A dual-band divide-by-2 quadrature injection-locked frequency divider (QILFD) is proposed to achieve high-speed, low power, wide-locking range, and accurate quadrature output phases. The QILFD consists of two dual-resonance differential voltage controlled oscillators and four coupling NMOS injectors in a ring configuration. The injectors are used as coupling devices of two differential ILFDs and are also used as common source amplifiers. The proposed QILFD has been implemented with the TSMC 90 nm CMOS technology and the core power consumption is 2.31 mW at the dc drain-source bias of 0.5 V. At the input power of 0 dBm, the low-band and high-band divide-by-2 operation ranges are respectively from 7.0 GHz to 10.1 GHz and 19.8 GHz to 24.6 GHz.

In this paper, a 1.8-V 10-bit 100,MS/s successive approximation register (SAR) analog-to-digital converter (ADC) simulated in a TSMC 0.18-$mu$m CMOS process is presented. By applying ten comparators followed by an asynchronous trigger logic, the proposed SAR ADC achieves high speed operation. Compared to the conventional SAR ADC, there is no significant delay in the digital feedback logic in this design. With the sampling rate limited only by the ten delays of the capacitor DAC settling and comparators quantization, the proposed SAR ADC achieves a peak SNDR of 61.2,dB at 100,MS/s and 80,MS/s, consuming 3.2,mW and 3.1,mW respectively.

A dual band 0.18 µm CMOS LC-tank injection locked frequency divider (ILFD) is proposed. The ILFD circuit is realized with a cross-coupled pMOS LC-tank oscillator with an inductor switch for frequency band selection. The self-oscillating VCO is injection-locked by nth-harmonic input to obtain the division factor of n. The division ratio of 1, 2, and 3 has been found for the proposed ILFD. Measurement results show that at the supply voltage of 1.1 V, the free-running frequency is from 2.28(3.09) GHz to 2.78(3.72) GHz for the low- (high-) frequency band. The power consumption of the ILFD core is 3.7 mW (6.2 mW) at low (high) band. The total area including the output buffer and the pads is 0.8410.764 mm2.