This paper proposes a wide-locking range divide-by-3 frequency divider employing 3D helical inductors fabricated in the 0.18-µm 1P6M CMOS technology. The divider consists of an nMOS cross-coupled LC oscillator and two injection MOSFETs in series with the cross-coupled NMOSFETs, and the LC resonator is composed of two 3D helical inductors and varactors. The aim of using 3D inductor is to reduce chip size. At the supply voltage of 1.2 V, the divider free-running frequency is tunable from 2.1 GHz to 2.6 GHz, and at the incident power of 0 dBm the locking range is about 2.11 GHz (29.16%), from the incident frequency 5.99 GHz to 8.1 GHz. The core power consumption is 4.56 mW. The die area is 0.664
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Sheng-Lyang JANG, Chia-Wei CHANG, Chien-Feng LEE, Jhin-Fang HUANG, "Divide-by-3 LC Injection Locked Frequency Divider Implemented with 3D Inductors" in IEICE TRANSACTIONS on Electronics,
vol. E91-C, no. 6, pp. 956-962, June 2008, doi: 10.1093/ietele/e91-c.6.956.
Abstract: This paper proposes a wide-locking range divide-by-3 frequency divider employing 3D helical inductors fabricated in the 0.18-µm 1P6M CMOS technology. The divider consists of an nMOS cross-coupled LC oscillator and two injection MOSFETs in series with the cross-coupled NMOSFETs, and the LC resonator is composed of two 3D helical inductors and varactors. The aim of using 3D inductor is to reduce chip size. At the supply voltage of 1.2 V, the divider free-running frequency is tunable from 2.1 GHz to 2.6 GHz, and at the incident power of 0 dBm the locking range is about 2.11 GHz (29.16%), from the incident frequency 5.99 GHz to 8.1 GHz. The core power consumption is 4.56 mW. The die area is 0.664
URL: https://global.ieice.org/en_transactions/electronics/10.1093/ietele/e91-c.6.956/_p
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@ARTICLE{e91-c_6_956,
author={Sheng-Lyang JANG, Chia-Wei CHANG, Chien-Feng LEE, Jhin-Fang HUANG, },
journal={IEICE TRANSACTIONS on Electronics},
title={Divide-by-3 LC Injection Locked Frequency Divider Implemented with 3D Inductors},
year={2008},
volume={E91-C},
number={6},
pages={956-962},
abstract={This paper proposes a wide-locking range divide-by-3 frequency divider employing 3D helical inductors fabricated in the 0.18-µm 1P6M CMOS technology. The divider consists of an nMOS cross-coupled LC oscillator and two injection MOSFETs in series with the cross-coupled NMOSFETs, and the LC resonator is composed of two 3D helical inductors and varactors. The aim of using 3D inductor is to reduce chip size. At the supply voltage of 1.2 V, the divider free-running frequency is tunable from 2.1 GHz to 2.6 GHz, and at the incident power of 0 dBm the locking range is about 2.11 GHz (29.16%), from the incident frequency 5.99 GHz to 8.1 GHz. The core power consumption is 4.56 mW. The die area is 0.664
keywords={},
doi={10.1093/ietele/e91-c.6.956},
ISSN={1745-1353},
month={June},}
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TY - JOUR
TI - Divide-by-3 LC Injection Locked Frequency Divider Implemented with 3D Inductors
T2 - IEICE TRANSACTIONS on Electronics
SP - 956
EP - 962
AU - Sheng-Lyang JANG
AU - Chia-Wei CHANG
AU - Chien-Feng LEE
AU - Jhin-Fang HUANG
PY - 2008
DO - 10.1093/ietele/e91-c.6.956
JO - IEICE TRANSACTIONS on Electronics
SN - 1745-1353
VL - E91-C
IS - 6
JA - IEICE TRANSACTIONS on Electronics
Y1 - June 2008
AB - This paper proposes a wide-locking range divide-by-3 frequency divider employing 3D helical inductors fabricated in the 0.18-µm 1P6M CMOS technology. The divider consists of an nMOS cross-coupled LC oscillator and two injection MOSFETs in series with the cross-coupled NMOSFETs, and the LC resonator is composed of two 3D helical inductors and varactors. The aim of using 3D inductor is to reduce chip size. At the supply voltage of 1.2 V, the divider free-running frequency is tunable from 2.1 GHz to 2.6 GHz, and at the incident power of 0 dBm the locking range is about 2.11 GHz (29.16%), from the incident frequency 5.99 GHz to 8.1 GHz. The core power consumption is 4.56 mW. The die area is 0.664
ER -