Millimeter-waves integrated circuits offer a unique opportunity for a holistic design approach encompassing RF, analog, and digital, as well as radiation and electromagnetics. The ability to deal with the complete system covering a broad range from the digital circuitry to on-chip antennas and everything in between offers unparalleled opportunities for completely new architectures and topologies, which were previously impossible due the traditional partitioning of various blocks in conventional design. This can open a plethora of new architectural and system level innovation within the integrated circuit platform. This paper reviews some of the challenges and opportunities for mm-wave ICs and presents several solutions to them.

This paper reviews techniques for digitally assisted pipeline ADCs. Errors of pipeline ADCs originated by capacitor mismatch, finite amplifier gain, incomplete settling and offset can be corrected in digital-domain foreground or background calibrations. In foreground calibrations, the errors are measured by reconfiguration of the building blocks of pipeline ADC or using an INL plot without reconfiguration. In background calibrations, the errors are measured with random signal and continuously corrected while simultaneously performing the normal A/D conversions. Techniques for measuring and correcting the errors at foreground and background are reviewed and a unified approach to the description of the principle of background calibration of gain errors is presented.

This paper presents a triple-band WCDMA direct conversion receiver (DCR) IC that needs a small number of off-chip components and control signals from digital baseband (DBB) IC. The DCR IC consists of 3 quadrature demodulators (QDEMs) with on-chip impedance matching circuit and an analog baseband block (ABB) that contains a low-pass filter (LPF) with f_c automatic tuning circuit using no off-chip components and a linear-in-dB variable-gain amplifier (VGA) with on-chip analog high-pass filter (HPF). In order to make use of DBB control-free DC offset canceler, the DCR is designed to avoid large gain change under large interference that causes long transient response. In order to realize that characteristic without increasing quiescent current, the QDEM is used that employs class AB input stage and low-noise common mode feedback (CMFB) output stage. The DCR IC was fabricated in a SiGe BiCMOS process and occupies about 2.9 mm3.0 mm. The DCR needs SAW filters only for off-chip components and a gain control signal from DBB IC for AGC loop. The IIP3 of over -4.4 dBm for small signal input level and that of over +1.9 dBm for large signal input level are achieved. The gain compression of the desired signal is less than 0.3 dB for ACS Case-II condition.

A low distortion and low noise differential amplifier using the difference between the even- and odd-mode impedances is proposed. In order to realize an amplifier with high OIP3 and low NF characteristics, the impedance of the bias circuit should be low (<300 Ω) at the difference frequency and high (>4 kΩ) at the carrier frequency. Although the frequency response of the bias circuit impedance can only meet these conditions with difficulty, owing to the 20 MHz Tx signal bandwidth for 3G LTE, the proposed amplifier can achieve the impedance difference using the properties of a differential configuration where the difference frequency signal is the even-mode and the carrier frequency is the odd-mode. It has been demonstrated that the NF of the proposed amplifier, which has been fabricated in 0.18 µm SiGe BiCMOS technology operating at 2.14 GHz, can be kept to 1.6 dB or less and an OIP3 of 9.0 dBm can be achieved, which is 3 dB higher than that of a conventional amplifier, in the condition where the power gain is greater than 18 dB.

RF Variable Gain Amplifiers (RF-VGA) are important components for integrated TV broadcast receivers. Analog and digital controlled RF-VGAs are compared in terms of linearity and an AGC loop architecture suitable for digitally controlled RF-VGA is proposed. Further linearity enhancement applicable for CMOS implementation is also discussed.

This paper describes a novel high-Q active inductor circuit configuration composed of an operational transconductance amplifier (OTA) and an input RC network. Due to the phase rotation made by the input RC network, the active inductor circuit provides high-Q inductive impedance at higher frequencies. According to circuit simulation with design-kit of a 90-GHz-f_T SiGe HBT technology, an inductance of more than 0.53 nH and Q of more than 80 can be obtained at quasi-millimeter-wave frequency, 24 GHz. The Q value is tunable by controlling the transconductance of the OTA. These features are also ensured by means of measurements of fabricated active inductor circuit. Since the active inductor circuit needs small chip area, which is 25% of a conventional passive inductor, the proposed active inductor contributes to implement a cost-effective high-Q notch filter for frequencies up to quasi-millimeter-wave frequencies.

In this paper the transfer function of a system with windowed current integration is discussed. This kind of integration is usually used in a sampling mixer and the current is generated by a transconductance amplifier (TA). The parasitic capacitance (C_p) and the output resistance of the TA (R_o,TA) before the sampling mixer heavily affect the performance. Calculations based on a model including the parasitic capacitance and the output resistance of the TA is carried out. Calculation results show that due to the parasitic capacitance, a notch at the sampling frequency appears, which is very harmful because it causes the gain near the sampling frequency to decrease greatly. The output resistance of the TA makes the depth of the notches shallow and decreases the gain near the sampling frequency. To suppress the effect of C_p and R_o,TA, an operational amplifier is introduced in parallel with the sampling capacitance (C_s). Simulation results show that there is a 17 dB gain increase while C_s is 1,pF, g_m is 9,mS, N is 8 with a clock rate of 800,MHz.

This paper presents a very wideband active RC polyphase filter (ARCPF). We propose a unit section of the ARCPF, which is an ordinary RCPF followed by opamps with parallel RC feedback. In the proposed unit section, pole and zero can be assigned independently. By using the unit ARCPFs, a very wideband image rejection filter can be realized by cascading the sections, which can greatly reduce the element value spread. To realize this, CMOS inverter based fully differential OTA which can operate under low supply voltage is also presented. This paper describes a six-stage active RC polyphase filter with 1-100 MHz passband in 0.18 µm CMOS technology.

For wireless receivers, low-power 1.2-V 12-bit 100-MSPS pipeline ADCs are fabricated in 90-nm CMOS technology. To achieve low-power dissipation at 1.2 V without the degradation of SNR, the configuration of 2.5 bit/stage is employed with an I/Q amplifier sharing technique. Furthermore, single-stage pseudo-differential amplifiers are used in a Sample-and-Hold (S/H) circuit and a 1st Multiplying Digital-to-Analog Converter (MDAC). The pseudo-differential amplifier with two-gain-stage transimpedance gain-boosting amplifiers realizes high DC gain of more than 90 dB with low power. The measured SNR of the 100-MSPS ADC is 66.7 dB at 1.2-V supply. Under that condition, each ADC dissipates only 55 mW.

This paper proposes a low power and high speed track and hold circuit (T/H circuit) based on the two-stage structure. The proposed circuit consists of two internal T/H circuits connected in cascade. The first T/H circuit converts an input signal into a step voltage and it is applied to the following second T/H circuit which drives large load capacitors and consumes large power. Applying the step voltage to the second T/H circuit prevents the second T/H circuit from charging and discharging its load capacitor during an identical track phase and enables low power operation. Thanks to the two-stage structure the proposed T/H circuit can save 29% of the power consumption compared with the conventional one. An optimum design procedure of the proposed two stage T/H circuit is explained and its validity is confirmed by HSPICE simulations.

A high-speed serial, 10-Gb/s, passive optical network (PON) is a good candidate for a future PON system. However, there are several issues to be solved in extending the physical speed to 10 Gb/s. The issues focused on here are not only the data rate, which is eight times higher than that of a conventional GE-PON, but also the instantaneous amplification and synchronization of AC-coupling burst-input data without a reset signal. An input amplifier with data-edge detection can both detect level-varying input due to AC-coupling and respond to the first bit of a burst packet. Another issue discussed here is tolerance to long consecutive identical digits (CIDs). A burst-mode clock-and-data recovery (CDR) using dual gated VCOs (G-VCOs) is designed for 10-Gb/s operation. The relation between the frequency difference of the dual G-VCOs and CID tolerance is derived with a frequency tunable G-VCO circuit. The burst-mode CDR IC is implemented in a 0.13-µm CMOS process. It successfully operates at a data rate of 10.3125 Gb/s. The CDR IC using the edge-detection input amplifier and the G-VCO CDR core achieves amplification and synchronization in 0.2 ns with AC-coupling without a reset signal. The IC also demonstrates 1001 bits of CID tolerance, which is more than enough tolerance for 65-bit CIDs in the 64B/66B code of 10 Gigabit Ethernet. Measured data suggest that dual G-VCOs on a die have over a 20-MHz frequency difference and that the frequency adjusting between the G-VCOs is effective for increasing CID tolerance.

A new spread spectrum clock generator (SSCG) using two-point delta-sigma modulation is presented in this paper. Not only the divider is varied, but also the voltage controlled oscillator is modulated. This technique can enhance the modulation bandwidth so that the effect of EMI suppression is improved with lower order ΣΔ modulator and can simultaneously optimize the jitter and the modulation profile. In addition, the method of two-path is applied to the loop filter to reduce the capacitance value such that the total integration can be achieved. The proposed SSCG has been fabricated in a 0.35 µm CMOS process. The clock of 400 MHz with center spread ratios of 1.25% and 2.5% are verified. The peak EMI reduction is 19.73 dB for the case of 2.5%. The size of chip area is 0.900.89 mm².

Analysis of resonance frequency in shorted transmission lines with inserted capacitor has been made. The analysis shows a resonance frequency dependence on capacitance position on a shorted transmission line. Two analysis methods are presented to predict the resonance frequency and understand how the inserted capacitor affects the resonance frequency of the shorted transmission line. Using this knowledge we propose a new structure for digital controlled oscillators utilizing the capacitance's sensitivity dependence on position of the shorted transmission line to increase the frequency resolution. A 9 GHz transmission line based digital controlled oscillator was designed and fabricated as a proof of concept. Measured results show that more than 100 times frequency step resolution increase is possible utilizing the same tuning capacitor size located at different points on the transmission line.

A cross-coupled charge pump with internal pumping capacitor, which is advantageous from a point of minimizing TFT-LCD driver IC module, is newly proposed in this paper. By using NMOS and PMOS diodes connected to boosting nodes from VIN nodes, the pumping node is precharged to the same value at the pumping node in starting pumping. Since the first-stage charge pump is designed differently from the other stage pumps, a back current of pumped charge from charge pumping node to input stage is prevented. As a pumping clock driver is located in front of pumping capacitor, the driving capacity is improved by reducing a voltage drop of the pumping clock line from parasitic resistor. Finally, a layout area is decreased more compared with the conventional cross-coupled charge pump by using a stack-MIM capacitor. A proposed charge pump for TFT-LCD driver IC is designed with 0.13 µm triple-well DDI process, fabricated, and tested.

Impacts of electromagnetic (EM) interference (immunity) on operation of LSI circuits in a QFP-packaged and PCB-mounted environment are studied. EM power injection to a power-supply system leads to malfunction, where the power is translated into voltage bounces through combined on- and off- chip impedances, affecting power supply and ground, as well as signal nodes in a die, seen from on-chip waveform measurements. A lumped power-supply impedance model and the minimum amplitude of voltage bounce induced by EM power for malfunction, both of which can be derived from external measurements to a given packaged LSI, formulate an EM interference model that is helpful in the PCB design toward high immunity. The technique can be generally applied to systems-on-chip applications.

A three-phase complex filter for a balanced three-phase analog signal processing is proposed. The proposed three-phase active-RC Tow-Thomas biquad complex filter can reduce total resistance by 10 percent, total capacitance by 25 percent, and power consumption by 22 percent compared to a conventional fully differential quadrature complex one.

Two dual-band bandpass filters (BPFs) based on the doubly parallel-coupled stepped impedance resonators (SIRs) structures have been proposed in this paper. The coupled-SIRs with/without open-stub-loads are introduced in the filter design. The dual-band filters exhibiting multiple zeros design operate at 2.45/5.2-GHz for the WLAN applications. Two three-staged filters composed of four SIRs have been proposed with the tapped-line adapted in the I/O sections. A five-staged filter is constructed based on the same design principle to achieve a better band-rejection. The proposed filters have the advantages of a much wider bandwidth in both the passbands without sacrificing the passband's insertion loss and passband flatness. The design procedure for a conventional parallel-coupled microstrip lines model is still suitable to design the proposed filters. The proposed filters have achieved almost twice the bandwidth of a conventional parallel-coupled lines configuration under the same design parameters. The experiments have been conducted to verify filter performance. Measured results are in good agreement with the full-wave simulation results.

This paper proposes a wide-locking range divide-by-3 frequency divider employing 3D helical inductors fabricated in the 0.18-µm 1P6M CMOS technology. The divider consists of an nMOS cross-coupled LC oscillator and two injection MOSFETs in series with the cross-coupled NMOSFETs, and the LC resonator is composed of two 3D helical inductors and varactors. The aim of using 3D inductor is to reduce chip size. At the supply voltage of 1.2 V, the divider free-running frequency is tunable from 2.1 GHz to 2.6 GHz, and at the incident power of 0 dBm the locking range is about 2.11 GHz (29.16%), from the incident frequency 5.99 GHz to 8.1 GHz. The core power consumption is 4.56 mW. The die area is 0.6640.831 mm².

The surface amino groups of plasma-polymerized films prepared from various nitrogen-containing monomers were quantitatively characterized for bioelectronic and biomedical applications. X-ray photoelectron spectroscopy (XPS) measurements were conducted on two kinds of surfaces: pristine surfaces of plasma-polymerized film prepared using various nitrogen-containing monomers, and theirs surfaces whose amino groups had been derivatized by a primary-amine-selective reagent carrying an XPS label. The XPS data showed that the maximum surface density of amino groups for this film was 8.410¹³ cm^-2. Amino groups constituted 14-64% of all surface nitrogen atoms (NH/N), depending on the monomer used.

This paper proposes an accurate modeling method of the copper interconnect cross-section in which the width and thickness dependence on layout patterns and density caused by processes (CMP, etching, sputtering, lithography, and so on) are fully incorporated and universally expressed. In addition, we have developed specific test patterns for the model parameters extraction, and an efficient extraction flow. We have extracted the model parameters for 0.15 µm CMOS using this method and confirmed that 10% τpd error normally observed with conventional LPE (Layout Parameters Extraction) was completely dissolved. Moreover, it is verified that the model can be applied to more advanced technologies (90 nm, 65 nm and 55 nm CMOS). Since the interconnect delay variations due to the processes constitute a significant part of what have conventionally been treated as random variations, use of the proposed model could enable one to greatly narrow the guardbands required to guarantee a desired yield, thereby facilitating design closure.

Techniques for patterned modification of substrate surfaces are important for forming microarrays on protein chips. A hexamethyldisiloxane plasma-polymerized film (HMDS PPF) was deposited on a glass substrate and the resulting surface was partially modified by subsequent nitrogen plasma treatment with a patterned shadow mask. When surface adsorption of an antibody protein (F(ab')₂ fragment of anti-human immunoglobulin G) was visualized by fluorescence microscopy, distinct 8080 µm² square spots were observed, surrounded by a non-fluorescent 80 µm-wide grid. This pattern could be attributed to proteins selectively adsorbed onto the nitrogen plasma-treated regions but not onto the surface of pristine HMDS PPF. This provided a simple fabrication method of protein patterning.