Accurate Modeling Method for Cu Interconnect

Kenta YAMADA; Hiroshi KITAHARA; Yoshihiko ASAI; Hideo SAKAMOTO; Norio OKADA; Makoto YASUDA; Noriaki ODA; Michio SAKURAI; Masayuki HIROI; Toshiyuki TAKEWAKI; Sadayuki OHNISHI; Manabu IGUCHI; Hiroyasu MINDA; Mieko SUZUKI

doi:10.1093/ietele/e91-c.6.968

Accurate Modeling Method for Cu Interconnect

Full Text Views

0

Cite this

Summary :

This paper proposes an accurate modeling method of the copper interconnect cross-section in which the width and thickness dependence on layout patterns and density caused by processes (CMP, etching, sputtering, lithography, and so on) are fully incorporated and universally expressed. In addition, we have developed specific test patterns for the model parameters extraction, and an efficient extraction flow. We have extracted the model parameters for 0.15 µm CMOS using this method and confirmed that 10% τpd error normally observed with conventional LPE (Layout Parameters Extraction) was completely dissolved. Moreover, it is verified that the model can be applied to more advanced technologies (90 nm, 65 nm and 55 nm CMOS). Since the interconnect delay variations due to the processes constitute a significant part of what have conventionally been treated as random variations, use of the proposed model could enable one to greatly narrow the guardbands required to guarantee a desired yield, thereby facilitating design closure.

Publication: IEICE TRANSACTIONS on Electronics Vol.E91-C No.6 pp.968-977

Publication Date: 2008/06/01

Publicized

Online ISSN: 1745-1353

DOI: 10.1093/ietele/e91-c.6.968

Type of Manuscript: PAPER

Category: Semiconductor Materials and Devices

Cite this

Copy

Kenta YAMADA, Hiroshi KITAHARA, Yoshihiko ASAI, Hideo SAKAMOTO, Norio OKADA, Makoto YASUDA, Noriaki ODA, Michio SAKURAI, Masayuki HIROI, Toshiyuki TAKEWAKI, Sadayuki OHNISHI, Manabu IGUCHI, Hiroyasu MINDA, Mieko SUZUKI, "Accurate Modeling Method for Cu Interconnect" in IEICE TRANSACTIONS on Electronics, vol. E91-C, no. 6, pp. 968-977, June 2008, doi: 10.1093/ietele/e91-c.6.968.
Abstract: This paper proposes an accurate modeling method of the copper interconnect cross-section in which the width and thickness dependence on layout patterns and density caused by processes (CMP, etching, sputtering, lithography, and so on) are fully incorporated and universally expressed. In addition, we have developed specific test patterns for the model parameters extraction, and an efficient extraction flow. We have extracted the model parameters for 0.15 µm CMOS using this method and confirmed that 10% τpd error normally observed with conventional LPE (Layout Parameters Extraction) was completely dissolved. Moreover, it is verified that the model can be applied to more advanced technologies (90 nm, 65 nm and 55 nm CMOS). Since the interconnect delay variations due to the processes constitute a significant part of what have conventionally been treated as random variations, use of the proposed model could enable one to greatly narrow the guardbands required to guarantee a desired yield, thereby facilitating design closure.
URL: https://global.ieice.org/en_transactions/electronics/10.1093/ietele/e91-c.6.968/_p

Copy

@ARTICLE{e91-c_6_968,
author={Kenta YAMADA, Hiroshi KITAHARA, Yoshihiko ASAI, Hideo SAKAMOTO, Norio OKADA, Makoto YASUDA, Noriaki ODA, Michio SAKURAI, Masayuki HIROI, Toshiyuki TAKEWAKI, Sadayuki OHNISHI, Manabu IGUCHI, Hiroyasu MINDA, Mieko SUZUKI, },
journal={IEICE TRANSACTIONS on Electronics},
title={Accurate Modeling Method for Cu Interconnect},
year={2008},
volume={E91-C},
number={6},
pages={968-977},
abstract={This paper proposes an accurate modeling method of the copper interconnect cross-section in which the width and thickness dependence on layout patterns and density caused by processes (CMP, etching, sputtering, lithography, and so on) are fully incorporated and universally expressed. In addition, we have developed specific test patterns for the model parameters extraction, and an efficient extraction flow. We have extracted the model parameters for 0.15 µm CMOS using this method and confirmed that 10% τpd error normally observed with conventional LPE (Layout Parameters Extraction) was completely dissolved. Moreover, it is verified that the model can be applied to more advanced technologies (90 nm, 65 nm and 55 nm CMOS). Since the interconnect delay variations due to the processes constitute a significant part of what have conventionally been treated as random variations, use of the proposed model could enable one to greatly narrow the guardbands required to guarantee a desired yield, thereby facilitating design closure.},
keywords={},
doi={10.1093/ietele/e91-c.6.968},
ISSN={1745-1353},
month={June},}

Copy

TY - JOUR
TI - Accurate Modeling Method for Cu Interconnect
T2 - IEICE TRANSACTIONS on Electronics
SP - 968
EP - 977
AU - Kenta YAMADA
AU - Hiroshi KITAHARA
AU - Yoshihiko ASAI
AU - Hideo SAKAMOTO
AU - Norio OKADA
AU - Makoto YASUDA
AU - Noriaki ODA
AU - Michio SAKURAI
AU - Masayuki HIROI
AU - Toshiyuki TAKEWAKI
AU - Sadayuki OHNISHI
AU - Manabu IGUCHI
AU - Hiroyasu MINDA
AU - Mieko SUZUKI
PY - 2008
DO - 10.1093/ietele/e91-c.6.968
JO - IEICE TRANSACTIONS on Electronics
SN - 1745-1353
VL - E91-C
IS - 6
JA - IEICE TRANSACTIONS on Electronics
Y1 - June 2008
AB - This paper proposes an accurate modeling method of the copper interconnect cross-section in which the width and thickness dependence on layout patterns and density caused by processes (CMP, etching, sputtering, lithography, and so on) are fully incorporated and universally expressed. In addition, we have developed specific test patterns for the model parameters extraction, and an efficient extraction flow. We have extracted the model parameters for 0.15 µm CMOS using this method and confirmed that 10% τpd error normally observed with conventional LPE (Layout Parameters Extraction) was completely dissolved. Moreover, it is verified that the model can be applied to more advanced technologies (90 nm, 65 nm and 55 nm CMOS). Since the interconnect delay variations due to the processes constitute a significant part of what have conventionally been treated as random variations, use of the proposed model could enable one to greatly narrow the guardbands required to guarantee a desired yield, thereby facilitating design closure.
ER -