Quadrature Hartley VCO and Injection-Locked Frequency Divider

Sheng-Lyang JANG; Chia-Wei CHANG; Sheng-Chien WU; Chien-Feng LEE; Lin-yen TSAI; Jhin-Fang HUANG

doi:10.1093/ietele/e91-c.8.1371

Quadrature Hartley VCO and Injection-Locked Frequency Divider

Sheng-Lyang JANG, Chia-Wei CHANG, Sheng-Chien WU, Chien-Feng LEE, Lin-yen TSAI, Jhin-Fang HUANG

Full Text Views

0

Cite this

Summary :

Novel low phase noise quadrature voltage-controlled oscillator (QVCO) and quadrature injection locked frequency divider (QILFD) with two coupled Hartley VCOs are proposed and implemented using the standard TSMC 0.18 µm CMOS 1P6M process. The QVCO employs pMOS as the core to reduce the up-conversion of low-frequency device noise to RF phase noise. It uses super-harmonic coupling technique to couple two differential Hartley VCOs and four small-size coupling transistors to set the directivity of quadrature output phases. At the 1.7 V supply voltage, the output phase noise of the QVCO is -124 dBc/Hz at 1 MHz offset frequency from the carrier frequency of 4.12 GHz, and the figure of merit is -185 dBc/Hz. At the supply voltage of 1.7 V, the total power consumption is 13.1 mW. At the supply voltage of 1.5 V, the tuning range of the free-running QILFD is from 2.05 GHz to 2.36 GHz, about 310 MHz, and the locking range of the ILFD is from 3.99 to 5.19 GHz, about 1.20 GHz, at the injection signal power of 0 dBm.

Publication: IEICE TRANSACTIONS on Electronics Vol.E91-C No.8 pp.1371-1374

Publication Date: 2008/08/01

Publicized

Online ISSN: 1745-1353

DOI: 10.1093/ietele/e91-c.8.1371

Type of Manuscript: LETTER

Category: Electronic Circuits

Cite this

Copy

Sheng-Lyang JANG, Chia-Wei CHANG, Sheng-Chien WU, Chien-Feng LEE, Lin-yen TSAI, Jhin-Fang HUANG, "Quadrature Hartley VCO and Injection-Locked Frequency Divider" in IEICE TRANSACTIONS on Electronics, vol. E91-C, no. 8, pp. 1371-1374, August 2008, doi: 10.1093/ietele/e91-c.8.1371.
Abstract: Novel low phase noise quadrature voltage-controlled oscillator (QVCO) and quadrature injection locked frequency divider (QILFD) with two coupled Hartley VCOs are proposed and implemented using the standard TSMC 0.18 µm CMOS 1P6M process. The QVCO employs pMOS as the core to reduce the up-conversion of low-frequency device noise to RF phase noise. It uses super-harmonic coupling technique to couple two differential Hartley VCOs and four small-size coupling transistors to set the directivity of quadrature output phases. At the 1.7 V supply voltage, the output phase noise of the QVCO is -124 dBc/Hz at 1 MHz offset frequency from the carrier frequency of 4.12 GHz, and the figure of merit is -185 dBc/Hz. At the supply voltage of 1.7 V, the total power consumption is 13.1 mW. At the supply voltage of 1.5 V, the tuning range of the free-running QILFD is from 2.05 GHz to 2.36 GHz, about 310 MHz, and the locking range of the ILFD is from 3.99 to 5.19 GHz, about 1.20 GHz, at the injection signal power of 0 dBm.
URL: https://global.ieice.org/en_transactions/electronics/10.1093/ietele/e91-c.8.1371/_p

Copy

@ARTICLE{e91-c_8_1371,
author={Sheng-Lyang JANG, Chia-Wei CHANG, Sheng-Chien WU, Chien-Feng LEE, Lin-yen TSAI, Jhin-Fang HUANG, },
journal={IEICE TRANSACTIONS on Electronics},
title={Quadrature Hartley VCO and Injection-Locked Frequency Divider},
year={2008},
volume={E91-C},
number={8},
pages={1371-1374},
abstract={Novel low phase noise quadrature voltage-controlled oscillator (QVCO) and quadrature injection locked frequency divider (QILFD) with two coupled Hartley VCOs are proposed and implemented using the standard TSMC 0.18 µm CMOS 1P6M process. The QVCO employs pMOS as the core to reduce the up-conversion of low-frequency device noise to RF phase noise. It uses super-harmonic coupling technique to couple two differential Hartley VCOs and four small-size coupling transistors to set the directivity of quadrature output phases. At the 1.7 V supply voltage, the output phase noise of the QVCO is -124 dBc/Hz at 1 MHz offset frequency from the carrier frequency of 4.12 GHz, and the figure of merit is -185 dBc/Hz. At the supply voltage of 1.7 V, the total power consumption is 13.1 mW. At the supply voltage of 1.5 V, the tuning range of the free-running QILFD is from 2.05 GHz to 2.36 GHz, about 310 MHz, and the locking range of the ILFD is from 3.99 to 5.19 GHz, about 1.20 GHz, at the injection signal power of 0 dBm.},
keywords={},
doi={10.1093/ietele/e91-c.8.1371},
ISSN={1745-1353},
month={August},}

Copy

TY - JOUR
TI - Quadrature Hartley VCO and Injection-Locked Frequency Divider
T2 - IEICE TRANSACTIONS on Electronics
SP - 1371
EP - 1374
AU - Sheng-Lyang JANG
AU - Chia-Wei CHANG
AU - Sheng-Chien WU
AU - Chien-Feng LEE
AU - Lin-yen TSAI
AU - Jhin-Fang HUANG
PY - 2008
DO - 10.1093/ietele/e91-c.8.1371
JO - IEICE TRANSACTIONS on Electronics
SN - 1745-1353
VL - E91-C
IS - 8
JA - IEICE TRANSACTIONS on Electronics
Y1 - August 2008
AB - Novel low phase noise quadrature voltage-controlled oscillator (QVCO) and quadrature injection locked frequency divider (QILFD) with two coupled Hartley VCOs are proposed and implemented using the standard TSMC 0.18 µm CMOS 1P6M process. The QVCO employs pMOS as the core to reduce the up-conversion of low-frequency device noise to RF phase noise. It uses super-harmonic coupling technique to couple two differential Hartley VCOs and four small-size coupling transistors to set the directivity of quadrature output phases. At the 1.7 V supply voltage, the output phase noise of the QVCO is -124 dBc/Hz at 1 MHz offset frequency from the carrier frequency of 4.12 GHz, and the figure of merit is -185 dBc/Hz. At the supply voltage of 1.7 V, the total power consumption is 13.1 mW. At the supply voltage of 1.5 V, the tuning range of the free-running QILFD is from 2.05 GHz to 2.36 GHz, about 310 MHz, and the locking range of the ILFD is from 3.99 to 5.19 GHz, about 1.20 GHz, at the injection signal power of 0 dBm.
ER -