IEICE TRANSACTIONS on Electronics
Source/Drain Engineering for High Performance Vertical MOSFET
Summary :
In this paper, Source/Drain (S/D) engineering for high performance (HP) Vertical MOSFET (V-MOSFET) in 3Xnm generation and its beyond is investigated, by using gradual S/D profile while degradation of driving current (ION) due to the parasitic series resistance (Rpara) is minimized through two-dimensional device simulation taking into account for gate-induced-drain-leakage (GIDL). In general, it is significant to reduce spreading resistance in the case of conventional Planar MOSFET. Therefore, in this study, we focused and analyzed the abruptness of diffusion layer that is still importance parameter in V-MOSFET. First, for improving the basic device performance such as subthreshold swing (SS), ION, and Rpara, S/D engineering is investigated. The dependency of device performance on S/D abruptness (σS/D) for various Lightly Doped Drain Extension (LDD) abruptness (σLDD) is analyzed. In this study, Spacer Length (LSP) is defined as a function of σS/D. As σS/D becomes smaller and S/D becomes more abrupt, LSP becomes shorter. SS depends on the σS/D rather than the σLDD. ION has the peak value of 1750 µA/µm at σS/D = 2 nm/dec. and σLDD=3 nm/dec. when the silicon pillar diameter (D) is 30 nm and the gate length (Lg) is 60 nm. As σS/D becomes small, higher ION is obtained due to reduction of Rpara while SS is degraded. However, when σS/D becomes too small in the short channel devices (Lg = 60 nm and Lg = 45 nm), ION is degraded because the leakage current due to GIDL is increased and reaches IOFF limit of 100 nA/µm. In addition, as σLDD becomes larger, larger ION is obtained in the case of Lg = 100 nm and Lg = 60 nm because channel length becomes shorter. On the other hand, in the case of Lg = 45 nm, as σLDD becomes larger, ION is degraded because short channel effect (SCE) becomes significant. Next, the dependency of the basic device performance on D is investigated. By slimming D from 30 nm to 10 nm, while SS is improved and approaches the ideal value of 60 mV/Decade, ION is degraded due to increase of on-resistance (Ron). From these results, it is necessary to reduce Rpara while IOFF meets limit of 100 nA/µm for designing S/D of HP V-MOSFET. Especially for the V-MOSFET in the 1Xnm generation and its beyond, the influence of the Rpara and GIDL on ION becomes more significant, and therefore, the trade-off between σS/D and ION has a much greater impact on S/D engineering of V-MOSFET.
- Publication
- IEICE TRANSACTIONS on Electronics Vol.E95-C No.5 pp.807-813
- Publication Date
- 2012/05/01
- Publicized
- Online ISSN
- 1745-1353
- DOI
- 10.1587/transele.E95.C.807
- Type of Manuscript
- Special Section PAPER (Special Section on Fundamentals and Applications of Advanced Semiconductor Devices)
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Takuya IMAMOTO, Tetsuo ENDOH, "Source/Drain Engineering for High Performance Vertical MOSFET" in IEICE TRANSACTIONS on Electronics,
vol. E95-C, no. 5, pp. 807-813, May 2012, doi: 10.1587/transele.E95.C.807.
Abstract: In this paper, Source/Drain (S/D) engineering for high performance (HP) Vertical MOSFET (V-MOSFET) in 3Xnm generation and its beyond is investigated, by using gradual S/D profile while degradation of driving current (ION) due to the parasitic series resistance (Rpara) is minimized through two-dimensional device simulation taking into account for gate-induced-drain-leakage (GIDL). In general, it is significant to reduce spreading resistance in the case of conventional Planar MOSFET. Therefore, in this study, we focused and analyzed the abruptness of diffusion layer that is still importance parameter in V-MOSFET. First, for improving the basic device performance such as subthreshold swing (SS), ION, and Rpara, S/D engineering is investigated. The dependency of device performance on S/D abruptness (σS/D) for various Lightly Doped Drain Extension (LDD) abruptness (σLDD) is analyzed. In this study, Spacer Length (LSP) is defined as a function of σS/D. As σS/D becomes smaller and S/D becomes more abrupt, LSP becomes shorter. SS depends on the σS/D rather than the σLDD. ION has the peak value of 1750 µA/µm at σS/D = 2 nm/dec. and σLDD=3 nm/dec. when the silicon pillar diameter (D) is 30 nm and the gate length (Lg) is 60 nm. As σS/D becomes small, higher ION is obtained due to reduction of Rpara while SS is degraded. However, when σS/D becomes too small in the short channel devices (Lg = 60 nm and Lg = 45 nm), ION is degraded because the leakage current due to GIDL is increased and reaches IOFF limit of 100 nA/µm. In addition, as σLDD becomes larger, larger ION is obtained in the case of Lg = 100 nm and Lg = 60 nm because channel length becomes shorter. On the other hand, in the case of Lg = 45 nm, as σLDD becomes larger, ION is degraded because short channel effect (SCE) becomes significant. Next, the dependency of the basic device performance on D is investigated. By slimming D from 30 nm to 10 nm, while SS is improved and approaches the ideal value of 60 mV/Decade, ION is degraded due to increase of on-resistance (Ron). From these results, it is necessary to reduce Rpara while IOFF meets limit of 100 nA/µm for designing S/D of HP V-MOSFET. Especially for the V-MOSFET in the 1Xnm generation and its beyond, the influence of the Rpara and GIDL on ION becomes more significant, and therefore, the trade-off between σS/D and ION has a much greater impact on S/D engineering of V-MOSFET.
URL: https://global.ieice.org/en_transactions/electronics/10.1587/transele.E95.C.807/_p
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@ARTICLE{e95-c_5_807,
author={Takuya IMAMOTO, Tetsuo ENDOH, },
journal={IEICE TRANSACTIONS on Electronics},
title={Source/Drain Engineering for High Performance Vertical MOSFET},
year={2012},
volume={E95-C},
number={5},
pages={807-813},
abstract={In this paper, Source/Drain (S/D) engineering for high performance (HP) Vertical MOSFET (V-MOSFET) in 3Xnm generation and its beyond is investigated, by using gradual S/D profile while degradation of driving current (ION) due to the parasitic series resistance (Rpara) is minimized through two-dimensional device simulation taking into account for gate-induced-drain-leakage (GIDL). In general, it is significant to reduce spreading resistance in the case of conventional Planar MOSFET. Therefore, in this study, we focused and analyzed the abruptness of diffusion layer that is still importance parameter in V-MOSFET. First, for improving the basic device performance such as subthreshold swing (SS), ION, and Rpara, S/D engineering is investigated. The dependency of device performance on S/D abruptness (σS/D) for various Lightly Doped Drain Extension (LDD) abruptness (σLDD) is analyzed. In this study, Spacer Length (LSP) is defined as a function of σS/D. As σS/D becomes smaller and S/D becomes more abrupt, LSP becomes shorter. SS depends on the σS/D rather than the σLDD. ION has the peak value of 1750 µA/µm at σS/D = 2 nm/dec. and σLDD=3 nm/dec. when the silicon pillar diameter (D) is 30 nm and the gate length (Lg) is 60 nm. As σS/D becomes small, higher ION is obtained due to reduction of Rpara while SS is degraded. However, when σS/D becomes too small in the short channel devices (Lg = 60 nm and Lg = 45 nm), ION is degraded because the leakage current due to GIDL is increased and reaches IOFF limit of 100 nA/µm. In addition, as σLDD becomes larger, larger ION is obtained in the case of Lg = 100 nm and Lg = 60 nm because channel length becomes shorter. On the other hand, in the case of Lg = 45 nm, as σLDD becomes larger, ION is degraded because short channel effect (SCE) becomes significant. Next, the dependency of the basic device performance on D is investigated. By slimming D from 30 nm to 10 nm, while SS is improved and approaches the ideal value of 60 mV/Decade, ION is degraded due to increase of on-resistance (Ron). From these results, it is necessary to reduce Rpara while IOFF meets limit of 100 nA/µm for designing S/D of HP V-MOSFET. Especially for the V-MOSFET in the 1Xnm generation and its beyond, the influence of the Rpara and GIDL on ION becomes more significant, and therefore, the trade-off between σS/D and ION has a much greater impact on S/D engineering of V-MOSFET.},
keywords={},
doi={10.1587/transele.E95.C.807},
ISSN={1745-1353},
month={May},}
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TY - JOUR
TI - Source/Drain Engineering for High Performance Vertical MOSFET
T2 - IEICE TRANSACTIONS on Electronics
SP - 807
EP - 813
AU - Takuya IMAMOTO
AU - Tetsuo ENDOH
PY - 2012
DO - 10.1587/transele.E95.C.807
JO - IEICE TRANSACTIONS on Electronics
SN - 1745-1353
VL - E95-C
IS - 5
JA - IEICE TRANSACTIONS on Electronics
Y1 - May 2012
AB - In this paper, Source/Drain (S/D) engineering for high performance (HP) Vertical MOSFET (V-MOSFET) in 3Xnm generation and its beyond is investigated, by using gradual S/D profile while degradation of driving current (ION) due to the parasitic series resistance (Rpara) is minimized through two-dimensional device simulation taking into account for gate-induced-drain-leakage (GIDL). In general, it is significant to reduce spreading resistance in the case of conventional Planar MOSFET. Therefore, in this study, we focused and analyzed the abruptness of diffusion layer that is still importance parameter in V-MOSFET. First, for improving the basic device performance such as subthreshold swing (SS), ION, and Rpara, S/D engineering is investigated. The dependency of device performance on S/D abruptness (σS/D) for various Lightly Doped Drain Extension (LDD) abruptness (σLDD) is analyzed. In this study, Spacer Length (LSP) is defined as a function of σS/D. As σS/D becomes smaller and S/D becomes more abrupt, LSP becomes shorter. SS depends on the σS/D rather than the σLDD. ION has the peak value of 1750 µA/µm at σS/D = 2 nm/dec. and σLDD=3 nm/dec. when the silicon pillar diameter (D) is 30 nm and the gate length (Lg) is 60 nm. As σS/D becomes small, higher ION is obtained due to reduction of Rpara while SS is degraded. However, when σS/D becomes too small in the short channel devices (Lg = 60 nm and Lg = 45 nm), ION is degraded because the leakage current due to GIDL is increased and reaches IOFF limit of 100 nA/µm. In addition, as σLDD becomes larger, larger ION is obtained in the case of Lg = 100 nm and Lg = 60 nm because channel length becomes shorter. On the other hand, in the case of Lg = 45 nm, as σLDD becomes larger, ION is degraded because short channel effect (SCE) becomes significant. Next, the dependency of the basic device performance on D is investigated. By slimming D from 30 nm to 10 nm, while SS is improved and approaches the ideal value of 60 mV/Decade, ION is degraded due to increase of on-resistance (Ron). From these results, it is necessary to reduce Rpara while IOFF meets limit of 100 nA/µm for designing S/D of HP V-MOSFET. Especially for the V-MOSFET in the 1Xnm generation and its beyond, the influence of the Rpara and GIDL on ION becomes more significant, and therefore, the trade-off between σS/D and ION has a much greater impact on S/D engineering of V-MOSFET.
ER -
English
