IEICE TRANSACTIONS on Electronics
A Schmitt Trigger Based SRAM with Vertical MOSFET
Summary :
In this paper, a Schmitt Trigger based 10T SRAM (ST 10T SRAM) cell with the vertical MOSFET is proposed for low supply voltage operation, and its impacts on cell size, stability and speed performance are investigated. The proposed ST 10T SRAM cell with the vertical MOSFET achieves smaller cell size than the ST 10T SRAM cell with the conventional planar MOSFET. Moreover, the proposed SRAM cell realizes large and constant static noise margin (SNM) against bottom node resistance of the vertical MOSFET without any architectural changes from the present 6T SRAM architecture. The proposed SRAM cell also suppresses the degradation of the read time of the ST 10T SRAM cell due to the back-bias effect free characteristic of the vertical MOSFET. The proposed ST 10T SRAM cell with the vertical MOSFET is a superior SRAM cell for low supply voltage operation with a small cell size, stable operation, and fast speed performance with the present 6T SRAM architecture.
- Publication
- IEICE TRANSACTIONS on Electronics Vol.E95-C No.5 pp.792-801
- Publication Date
- 2012/05/01
- Publicized
- Online ISSN
- 1745-1353
- DOI
- 10.1587/transele.E95.C.792
- Type of Manuscript
- Special Section PAPER (Special Section on Fundamentals and Applications of Advanced Semiconductor Devices)
- Category
Authors
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Hyoungjun NA, Tetsuo ENDOH, "A Schmitt Trigger Based SRAM with Vertical MOSFET" in IEICE TRANSACTIONS on Electronics,
vol. E95-C, no. 5, pp. 792-801, May 2012, doi: 10.1587/transele.E95.C.792.
Abstract: In this paper, a Schmitt Trigger based 10T SRAM (ST 10T SRAM) cell with the vertical MOSFET is proposed for low supply voltage operation, and its impacts on cell size, stability and speed performance are investigated. The proposed ST 10T SRAM cell with the vertical MOSFET achieves smaller cell size than the ST 10T SRAM cell with the conventional planar MOSFET. Moreover, the proposed SRAM cell realizes large and constant static noise margin (SNM) against bottom node resistance of the vertical MOSFET without any architectural changes from the present 6T SRAM architecture. The proposed SRAM cell also suppresses the degradation of the read time of the ST 10T SRAM cell due to the back-bias effect free characteristic of the vertical MOSFET. The proposed ST 10T SRAM cell with the vertical MOSFET is a superior SRAM cell for low supply voltage operation with a small cell size, stable operation, and fast speed performance with the present 6T SRAM architecture.
URL: https://global.ieice.org/en_transactions/electronics/10.1587/transele.E95.C.792/_p
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@ARTICLE{e95-c_5_792,
author={Hyoungjun NA, Tetsuo ENDOH, },
journal={IEICE TRANSACTIONS on Electronics},
title={A Schmitt Trigger Based SRAM with Vertical MOSFET},
year={2012},
volume={E95-C},
number={5},
pages={792-801},
abstract={In this paper, a Schmitt Trigger based 10T SRAM (ST 10T SRAM) cell with the vertical MOSFET is proposed for low supply voltage operation, and its impacts on cell size, stability and speed performance are investigated. The proposed ST 10T SRAM cell with the vertical MOSFET achieves smaller cell size than the ST 10T SRAM cell with the conventional planar MOSFET. Moreover, the proposed SRAM cell realizes large and constant static noise margin (SNM) against bottom node resistance of the vertical MOSFET without any architectural changes from the present 6T SRAM architecture. The proposed SRAM cell also suppresses the degradation of the read time of the ST 10T SRAM cell due to the back-bias effect free characteristic of the vertical MOSFET. The proposed ST 10T SRAM cell with the vertical MOSFET is a superior SRAM cell for low supply voltage operation with a small cell size, stable operation, and fast speed performance with the present 6T SRAM architecture.},
keywords={},
doi={10.1587/transele.E95.C.792},
ISSN={1745-1353},
month={May},}
Copy
TY - JOUR
TI - A Schmitt Trigger Based SRAM with Vertical MOSFET
T2 - IEICE TRANSACTIONS on Electronics
SP - 792
EP - 801
AU - Hyoungjun NA
AU - Tetsuo ENDOH
PY - 2012
DO - 10.1587/transele.E95.C.792
JO - IEICE TRANSACTIONS on Electronics
SN - 1745-1353
VL - E95-C
IS - 5
JA - IEICE TRANSACTIONS on Electronics
Y1 - May 2012
AB - In this paper, a Schmitt Trigger based 10T SRAM (ST 10T SRAM) cell with the vertical MOSFET is proposed for low supply voltage operation, and its impacts on cell size, stability and speed performance are investigated. The proposed ST 10T SRAM cell with the vertical MOSFET achieves smaller cell size than the ST 10T SRAM cell with the conventional planar MOSFET. Moreover, the proposed SRAM cell realizes large and constant static noise margin (SNM) against bottom node resistance of the vertical MOSFET without any architectural changes from the present 6T SRAM architecture. The proposed SRAM cell also suppresses the degradation of the read time of the ST 10T SRAM cell due to the back-bias effect free characteristic of the vertical MOSFET. The proposed ST 10T SRAM cell with the vertical MOSFET is a superior SRAM cell for low supply voltage operation with a small cell size, stable operation, and fast speed performance with the present 6T SRAM architecture.
ER -
English
