1-4hit |
Aromhack SAYSANASONGKHAM Satoshi FUKUMOTO
In this research, we investigated the reliability of a 1-out-of-2 system with two-stage repair comprising hardware restoration and data reconstruction modes. Hardware restoration is normally independently executed by two modules. In contrast, we assumed that one of the modules could omit data reconstruction by replicating the data from the module during normal operation. In this 1-out-of-2 system, the two modules mutually cooperated in the recovery mode. As a first step, an evaluation model using Markov chains was constructed to derive a reliability measure: “unavailability in steady state.” Numerical examples confirmed that the reliability of the system was improved by the use of two cooperating modules. As the data reconstruction time increased, the gains in terms of system reliability also increased.
In this study, a low-cost, power-saving and reliable Multiple Server Backup System (MSBS) was configured and tested. The MSBS is based on a Dynamic Backup Server System (DBSS) and is able to recover many different server functions. To configure the DBSS, the mode segmentation method is introduced to simplify system control design and improve applicability to other systems. Experiments based on a mail server showed that the DBSS has sufficient ability to deal with various types of issues, including software and hardware failures. Furthermore, it is important to evaluate the virtual server performance in recovering target server functions. The well-known clock time inaccuracy problem of the virtual server is solved using the network access method regardless of the failure.
Shinichiro YAMAGUCHI Tetsuaki NAKAMIKAWA Naoto MIYAZAKI Yuuichirou MORITA Yoshihiro MIYAZAKI Sakou ISHIKAWA
The fault tolerant computer (FTC) is applied as a communication or database server in the information service and computer aided process control fields. User requires of the FTC are to provide the current level of performance and software transparency needing no additional dedicated program for fault tolerance. To meet these requirements, we propose quadprocessor redundancy (QPR) architecture that combines dualRISC based duplicated CPUs integrating main memories, and duplicated I/O subsystems by using some additional hardware. Duplicated CPUs run under the instruction level synchronization (lock step operation) , and the duplicated I/O subsystems are managed by an operating system. When a fault is detected, the faulty CPU is isolated by hardware. User program is continuously executed by the remaining CPU. We applied the QPR to our UNIX servers, and achieved satisfactory levels of performance.
Kyoichi NAKASHIMA Hitoshi MATZNAGA
For systems in which the probability that an incorrect output is observed differs with input values, we adopt the redundant usage of n copies of identical systems which we call the n-redundant system. This paper presents a method to find the optimal redundancy of systems for minimizing the probability of dangerous errors. First, it is proved that a k-out-of-n redundancy or a mixture of two kinds of k-out-of-n redundancies minimizes the probability of D-errors under the condition that the probability of output errors including both dangerous errors and safe errors is below a specified value. Next, an algorithm is given to find the optimal series-parallel redundancy of systems by using the properties of the distance between two structure functions.