Quad-Processor Redundancy for a RISC-Based Fault Tolerant Computer
Summary :
The fault tolerant computer (FTC) is applied as a communication or database server in the information service and computer aided process control fields. User requires of the FTC are to provide the current level of performance and software transparency needing no additional dedicated program for fault tolerance. To meet these requirements, we propose quadprocessor redundancy (QPR) architecture that combines dualRISC based duplicated CPUs integrating main memories, and duplicated I/O subsystems by using some additional hardware. Duplicated CPUs run under the instruction level synchronization (lock step operation) , and the duplicated I/O subsystems are managed by an operating system. When a fault is detected, the faulty CPU is isolated by hardware. User program is continuously executed by the remaining CPU. We applied the QPR to our UNIX servers, and achieved satisfactory levels of performance.
- Publication
- IEICE TRANSACTIONS on Information Vol.E80-D No.1 pp.15-20
- Publication Date
- 1997/01/25
- Publicized
- Online ISSN
- DOI
- Type of Manuscript
- Special Section PAPER (Special Issue on Fault-Tolerant Computing)
- Category
- Redundancy Techniques
Authors
Shinichiro YAMAGUCHI
Tetsuaki NAKAMIKAWA
Naoto MIYAZAKI
Yuuichirou MORITA
Yoshihiro MIYAZAKI
Sakou ISHIKAWA
Keyword
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Shinichiro YAMAGUCHI, Tetsuaki NAKAMIKAWA, Naoto MIYAZAKI, Yuuichirou MORITA, Yoshihiro MIYAZAKI, Sakou ISHIKAWA, "Quad-Processor Redundancy for a RISC-Based Fault Tolerant Computer" in IEICE TRANSACTIONS on Information,
vol. E80-D, no. 1, pp. 15-20, January 1997, doi: .
Abstract: The fault tolerant computer (FTC) is applied as a communication or database server in the information service and computer aided process control fields. User requires of the FTC are to provide the current level of performance and software transparency needing no additional dedicated program for fault tolerance. To meet these requirements, we propose quadprocessor redundancy (QPR) architecture that combines dualRISC based duplicated CPUs integrating main memories, and duplicated I/O subsystems by using some additional hardware. Duplicated CPUs run under the instruction level synchronization (lock step operation) , and the duplicated I/O subsystems are managed by an operating system. When a fault is detected, the faulty CPU is isolated by hardware. User program is continuously executed by the remaining CPU. We applied the QPR to our UNIX servers, and achieved satisfactory levels of performance.
URL: https://global.ieice.org/en_transactions/information/10.1587/e80-d_1_15/_p
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@ARTICLE{e80-d_1_15,
author={Shinichiro YAMAGUCHI, Tetsuaki NAKAMIKAWA, Naoto MIYAZAKI, Yuuichirou MORITA, Yoshihiro MIYAZAKI, Sakou ISHIKAWA, },
journal={IEICE TRANSACTIONS on Information},
title={Quad-Processor Redundancy for a RISC-Based Fault Tolerant Computer},
year={1997},
volume={E80-D},
number={1},
pages={15-20},
abstract={The fault tolerant computer (FTC) is applied as a communication or database server in the information service and computer aided process control fields. User requires of the FTC are to provide the current level of performance and software transparency needing no additional dedicated program for fault tolerance. To meet these requirements, we propose quadprocessor redundancy (QPR) architecture that combines dualRISC based duplicated CPUs integrating main memories, and duplicated I/O subsystems by using some additional hardware. Duplicated CPUs run under the instruction level synchronization (lock step operation) , and the duplicated I/O subsystems are managed by an operating system. When a fault is detected, the faulty CPU is isolated by hardware. User program is continuously executed by the remaining CPU. We applied the QPR to our UNIX servers, and achieved satisfactory levels of performance.},
keywords={},
doi={},
ISSN={},
month={January},}
Copy
TY - JOUR
TI - Quad-Processor Redundancy for a RISC-Based Fault Tolerant Computer
T2 - IEICE TRANSACTIONS on Information
SP - 15
EP - 20
AU - Shinichiro YAMAGUCHI
AU - Tetsuaki NAKAMIKAWA
AU - Naoto MIYAZAKI
AU - Yuuichirou MORITA
AU - Yoshihiro MIYAZAKI
AU - Sakou ISHIKAWA
PY - 1997
DO -
JO - IEICE TRANSACTIONS on Information
SN -
VL - E80-D
IS - 1
JA - IEICE TRANSACTIONS on Information
Y1 - January 1997
AB - The fault tolerant computer (FTC) is applied as a communication or database server in the information service and computer aided process control fields. User requires of the FTC are to provide the current level of performance and software transparency needing no additional dedicated program for fault tolerance. To meet these requirements, we propose quadprocessor redundancy (QPR) architecture that combines dualRISC based duplicated CPUs integrating main memories, and duplicated I/O subsystems by using some additional hardware. Duplicated CPUs run under the instruction level synchronization (lock step operation) , and the duplicated I/O subsystems are managed by an operating system. When a fault is detected, the faulty CPU is isolated by hardware. User program is continuously executed by the remaining CPU. We applied the QPR to our UNIX servers, and achieved satisfactory levels of performance.
ER -
English
