To enhance fuel efficiency and lower manufacturing and maintenance costs, in-vehicle wireless networks can facilitate the weight reduction of vehicle wire harnesses. In this paper, we utilize the Impulse Radio-Ultra Wideband (IR-UWB) of IEEE 802.15.4a/z for in-vehicle wireless networks because of its excellent signal penetration and robustness in multipath environments. Since clear channel assessment is optional in this standard, we employ polling control as a multiple access control to prevent interference within the system. Therein, the preamble overhead is large in IR-UWB of IEEE 802.15.4a/z. Hence, aggregating as much sensor data as possible within each frame is more efficient. In this paper, we assume that reading out data from sensors and sending data to actuators is periodical and that their respective phases can be adjusted. Therefore, this paper proposes an integer linear programming-based scheduling algorithm that minimizes the number of transmitted frames by adjusting the read and write phases. Furthermore, we provide a heuristic algorithm that computes a sub-optimal but acceptable solution in a shorter time. Experimental validation shows that the data aggregation of the proposed algorithms is robust against interference.

An ASIC crypto processor optimized for the 254-bit prime-field optimal-ate pairing over Barreto-Naehrig (BN) curve is proposed. The data path of the proposed crypto processor is designed to compute five Fp2 operations, a multiplication, three addition/subtractions, and an inversion, simultaneously. We further propose a design methodology to automate the instruction scheduling by using a combinatorial optimization solver, with which the total cycle count is reduced to 1/2 compared with ever reported. The proposed crypto processor is designed and fabricated by using a 65nm silicon-on-thin-box (SOTB) CMOS process. The chip measurement result shows that the fabricated chip successfully computes a pairing in 0.185ms when a typical operating voltage of 1.20V is applied, which corresponds to 2.8× speed up compared to the current state-of-the-art pairing implementation on ASIC platform.