The maximum likelihood sequence estimator (MLSE) is usually implemented by the Viterbi algorithm (VA). The computational complexity of the VA grows exponentially with the length of the channel response. With some performance reduction, a decision-feedback equalizer (DFE) can be used to shorten the channel response. This greatly reduces the computational requirement for the VA. However, for many real-world applications, the complexity of the DFE/MLSE approach may be still too high. In this paper, we propose a constrained DFE that offers much lower VA computational complexity. The basic idea is to pose some constraints on the DFE such that the postcursors of the shortened channel response have only discrete values. As a result, the multiplication operations can be replaced by shift operations making the VA almost multiplication free. This will greatly facilitate the real world applications of the MLSE algorithm. Simulation results show that while the proposed algorithm basically offers the same performance as the original MLSE performance, the VA is much more efficient than the conventional approach.

This paper proposes a novel VLSI architecture capable of processing the Lempel-Ziv-based data compression algorithm very fast. The architecture is composed of five main blocks, i.e., a PE-based Match Block, a Consecutive Hit Checker, a Pointer Generator, a Length Generator, and a Code Packer. Flexibility of the PE-based structure makes it possible to adapt to various buffer sizes without any loss of speed or additional control overhead. Since it is designed as a VLSI-oriented architecture, it has simple control logic circuitry. It processes exactly one character per clock cycle and the update of a dictionary buffer is automatically done, therefore it does not require additional accumulated shift operations to prepare for the dictionary buffer. The shift operations have been major problems commonly found in most other architectures. When implemented with the currently available 0.5µm CMOS technology, it is proven by critical path analysis that the architecture can achieve over 100 mega samples (characters) per second with a clock frequency of 100 MHz. This is fast enough for real time data compression for many applications.

The purpose of this paper is to provide a practical tool for performing a shift operation in orthonormal compactly supported wavelet bases. This translation τ of a discrete sequence, where τ is a real number, is suitable for filter bank implementations. The shift operation in this realization is neither related to the analysis filters nor to the synthesis filters of the filter bank. Simulations were done on the Daubechis wavelets with 12 coefficients and on complex valued wavelets. For the latter ones a real input sequence was used and split up into two subsequences in order to gain computational efficiency.