We present circuit implementations for computing exponentials and logarithms suitable for rapid single-flux-quantum (RSFQ) logic. We propose hardware algorithms based on the sequential table-lookup (STL) method using the radix-2 signed-digit representation that achieve high-throughput, digit-serial calculations. The circuits are implemented by processing elements formed in systolic-array-like, regularly-aligned pipeline structures. The processing elements are composed of adders, shifters, and readouts of precomputed constants. The iterative calculations are fully overlapped, and throughputs approach the maximum throughput of serial processing. The circuit size for calculating significand parts is estimated to be approximately 5-10 times larger than that of a bit-serial floating-point adder or multiplier.

In 2000, Dimitrov, Jullien, and Miller proposed an efficient and simple double-exponentiation algorithm based on a signed-digit recoding algorithm. The average joint Hamming ratio (AJHR) was reduced from 0.556 to 0.534 by using the recoding algorithm. In this paper, the DJM recoding algorithm was extended to three types: the 3-digit sliding window, the 1-digit right-to-left sliding window, and the 1-digit left-to-right sliding window. The average joint Hamming ratios of the three cases were 0.521, 0.515, and 0.511, respectively.

A hardware algorithm for integer division is proposed. It is based on the radix-2 non-restoring division algorithm. Fast computation is achieved by the use of the radix-2 signed-digit (SD2) representation. The algorithm does not require normalization of the divisor, and hence, does not require an area-consuming leading-one (or zero) detection nor shifts of variable-amount. Combinational (unfolded) implementation of the algorithm yields a regularly structured array divider, and sequential implementation yields compact dividers.