High-Throughput Rapid Single-Flux-Quantum Circuit Implementations for Exponential and Logarithm Computation Using the Radix-2 Signed-Digit Representation
Summary :
We present circuit implementations for computing exponentials and logarithms suitable for rapid single-flux-quantum (RSFQ) logic. We propose hardware algorithms based on the sequential table-lookup (STL) method using the radix-2 signed-digit representation that achieve high-throughput, digit-serial calculations. The circuits are implemented by processing elements formed in systolic-array-like, regularly-aligned pipeline structures. The processing elements are composed of adders, shifters, and readouts of precomputed constants. The iterative calculations are fully overlapped, and throughputs approach the maximum throughput of serial processing. The circuit size for calculating significand parts is estimated to be approximately 5-10 times larger than that of a bit-serial floating-point adder or multiplier.
- Publication
- IEICE TRANSACTIONS on Electronics Vol.E99-C No.6 pp.703-709
- Publication Date
- 2016/06/01
- Publicized
- Online ISSN
- 1745-1353
- DOI
- 10.1587/transele.E99.C.703
- Type of Manuscript
- Special Section PAPER (Special Section on Cutting-Edge Technologies of Superconducting Electronics)
- Category
Authors
Masamitsu TANAKA
Nagoya University
Kazuyoshi TAKAGI
Kyoto University
Naofumi TAKAGI
Kyoto University
Keyword
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Masamitsu TANAKA, Kazuyoshi TAKAGI, Naofumi TAKAGI, "High-Throughput Rapid Single-Flux-Quantum Circuit Implementations for Exponential and Logarithm Computation Using the Radix-2 Signed-Digit Representation" in IEICE TRANSACTIONS on Electronics,
vol. E99-C, no. 6, pp. 703-709, June 2016, doi: 10.1587/transele.E99.C.703.
Abstract: We present circuit implementations for computing exponentials and logarithms suitable for rapid single-flux-quantum (RSFQ) logic. We propose hardware algorithms based on the sequential table-lookup (STL) method using the radix-2 signed-digit representation that achieve high-throughput, digit-serial calculations. The circuits are implemented by processing elements formed in systolic-array-like, regularly-aligned pipeline structures. The processing elements are composed of adders, shifters, and readouts of precomputed constants. The iterative calculations are fully overlapped, and throughputs approach the maximum throughput of serial processing. The circuit size for calculating significand parts is estimated to be approximately 5-10 times larger than that of a bit-serial floating-point adder or multiplier.
URL: https://global.ieice.org/en_transactions/electronics/10.1587/transele.E99.C.703/_p
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@ARTICLE{e99-c_6_703,
author={Masamitsu TANAKA, Kazuyoshi TAKAGI, Naofumi TAKAGI, },
journal={IEICE TRANSACTIONS on Electronics},
title={High-Throughput Rapid Single-Flux-Quantum Circuit Implementations for Exponential and Logarithm Computation Using the Radix-2 Signed-Digit Representation},
year={2016},
volume={E99-C},
number={6},
pages={703-709},
abstract={We present circuit implementations for computing exponentials and logarithms suitable for rapid single-flux-quantum (RSFQ) logic. We propose hardware algorithms based on the sequential table-lookup (STL) method using the radix-2 signed-digit representation that achieve high-throughput, digit-serial calculations. The circuits are implemented by processing elements formed in systolic-array-like, regularly-aligned pipeline structures. The processing elements are composed of adders, shifters, and readouts of precomputed constants. The iterative calculations are fully overlapped, and throughputs approach the maximum throughput of serial processing. The circuit size for calculating significand parts is estimated to be approximately 5-10 times larger than that of a bit-serial floating-point adder or multiplier.},
keywords={},
doi={10.1587/transele.E99.C.703},
ISSN={1745-1353},
month={June},}
Copy
TY - JOUR
TI - High-Throughput Rapid Single-Flux-Quantum Circuit Implementations for Exponential and Logarithm Computation Using the Radix-2 Signed-Digit Representation
T2 - IEICE TRANSACTIONS on Electronics
SP - 703
EP - 709
AU - Masamitsu TANAKA
AU - Kazuyoshi TAKAGI
AU - Naofumi TAKAGI
PY - 2016
DO - 10.1587/transele.E99.C.703
JO - IEICE TRANSACTIONS on Electronics
SN - 1745-1353
VL - E99-C
IS - 6
JA - IEICE TRANSACTIONS on Electronics
Y1 - June 2016
AB - We present circuit implementations for computing exponentials and logarithms suitable for rapid single-flux-quantum (RSFQ) logic. We propose hardware algorithms based on the sequential table-lookup (STL) method using the radix-2 signed-digit representation that achieve high-throughput, digit-serial calculations. The circuits are implemented by processing elements formed in systolic-array-like, regularly-aligned pipeline structures. The processing elements are composed of adders, shifters, and readouts of precomputed constants. The iterative calculations are fully overlapped, and throughputs approach the maximum throughput of serial processing. The circuit size for calculating significand parts is estimated to be approximately 5-10 times larger than that of a bit-serial floating-point adder or multiplier.
ER -
English
