The efficient squaring algorithm is an important role in large integer arithmetic. All multiplication algorithms can be used for squaring large integers, but their performance can be greatly improved by using the standard squaring algorithm. The standard squaring algorithm is quite well-known, but unfortunately there is an improper carry handling bug in it. Recently, Guajardo and Paar proposed a modified squaring algorithm to fix the bug in the standard squaring algorithm. In this paper, we first point out that there is still an error-indexing bug in the Guajardo-Paar squaring algorithm. Then, we propose a new efficient squaring algorithm that not only avoids the bugs in both the standard squaring algorithm and the Guajardo-Paar squaring algorithm but also improves the performance in squaring computation. Our analyses and our simulations indicate that the proposed squaring algorithm is about 2.5 times faster in comparison with the standard multiplication algorithm in Pentium Series CPU. The performance of 1024-bit RSA cryptosystem can be saved 34.3% by using the proposed squaring algorithm to replace the standard multiplication.

Recently, in the modem, the spread spectrum communication system and the software radio, Digital Signal Processor type Squaring Loop (DSP-squaring-loop) is employed in the demodulation of Binary Phase Shift Keying (BPSK) signal. The DSP-squaring-loop extracts the carrier signal that is used for the coherent detection. However, in case the Signal to Noise Ratio (SNR) is low, the DSP-Phase Locked Loop (DSP-PLL) can not pull in the frequency offset and the phase offset. In this paper, we propose a DSP-squaring-loop that is robust against noise and which uses the adaptive notch filter type frequency estimator and the adaptive Band Pass Filter (BPF). The proposed method can extract the carrier signal in the low SNR environment. The effectiveness of the proposed method is confirmed by the computer simulation results.

An emitter–coupled pair with a dynamic bias current and a source–coupled pair with a dynamic bias current are proposed as an exponential–law element and a square–law element that operate as a floating bipolar junction transistor (BJT) and a floating MOS field–effect transistor (MOSFET). In bipolar technology, a hyperbolic sine function circuit and a hyperbolic cosine function circuit are easily obtained by subtracting and summing the output currents of two symmetrical exponential–law elements with positive and negative input signals. In the same manner, an operational transconductance amplifier (OTA) and a squaring circuit are obtained by subtracting and summing the output currents of two symmetrical square-law elements with positive and negative input signals in CMOS technology. The proposed OTA and squaring circuit possess the widest input voltage range ever reported.