Efficient road-lane detection is expected to be achievable by application of the Hough transform (HT) which realizes high-accuracy straight-line extraction from images. The main challenge for HT-hardware implementation in actual applications is the trade-off optimization between accuracy maximization, power-dissipation reduction and real-time requirements. We report a HT-hardware architecture for road-lane detection with parallelized voting procedure, local maximum algorithm and FPGA-prototype implementation. Parallelization of the global design is realized on the basis of θ-value discretization in the Hough space. Four major hardware modules are developed for edge detection in the original video frames, computation of the characteristic edge-pixel values (ρ,θ) in Hough-space, voting procedure for each (ρ,θ) pair with parallel local-maximum-based peak voting-point extraction in Hough space to determine the detected straight lines. Implementation of a prototype system for real-time road-lane detection on a low-cost DE1 platform with a Cyclone II FPGA device was verified to be possible. An average detection speed of 135 frames/s for VGA (640x480)-frames was achieved at 50 MHz working frequency.