IEICE TRANSACTIONS on Information
Energy-Efficient Hardware Implementation of Road-Lane Detection Based on Hough Transform with Parallelized Voting Procedure and Local Maximum Algorithm
Summary :
Efficient road-lane detection is expected to be achievable by application of the Hough transform (HT) which realizes high-accuracy straight-line extraction from images. The main challenge for HT-hardware implementation in actual applications is the trade-off optimization between accuracy maximization, power-dissipation reduction and real-time requirements. We report a HT-hardware architecture for road-lane detection with parallelized voting procedure, local maximum algorithm and FPGA-prototype implementation. Parallelization of the global design is realized on the basis of θ-value discretization in the Hough space. Four major hardware modules are developed for edge detection in the original video frames, computation of the characteristic edge-pixel values (ρ,θ) in Hough-space, voting procedure for each (ρ,θ) pair with parallel local-maximum-based peak voting-point extraction in Hough space to determine the detected straight lines. Implementation of a prototype system for real-time road-lane detection on a low-cost DE1 platform with a Cyclone II FPGA device was verified to be possible. An average detection speed of 135 frames/s for VGA (640x480)-frames was achieved at 50 MHz working frequency.
- Publication
- IEICE TRANSACTIONS on Information Vol.E102-D No.6 pp.1171-1182
- Publication Date
- 2019/06/01
- Publicized
- 2019/03/05
- Online ISSN
- 1745-1361
- DOI
- 10.1587/transinf.2018EDP7279
- Type of Manuscript
- PAPER
- Category
- Image Processing and Video Processing
Authors
Jungang GUAN
Hiroshima University
Fengwei AN
Hiroshima University
Xiangyu ZHANG
Hiroshima University
Lei CHEN
Hiroshima University
Hans Jürgen MATTAUSCH
Hiroshima University
Keyword
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Jungang GUAN, Fengwei AN, Xiangyu ZHANG, Lei CHEN, Hans Jürgen MATTAUSCH, "Energy-Efficient Hardware Implementation of Road-Lane Detection Based on Hough Transform with Parallelized Voting Procedure and Local Maximum Algorithm" in IEICE TRANSACTIONS on Information,
vol. E102-D, no. 6, pp. 1171-1182, June 2019, doi: 10.1587/transinf.2018EDP7279.
Abstract: Efficient road-lane detection is expected to be achievable by application of the Hough transform (HT) which realizes high-accuracy straight-line extraction from images. The main challenge for HT-hardware implementation in actual applications is the trade-off optimization between accuracy maximization, power-dissipation reduction and real-time requirements. We report a HT-hardware architecture for road-lane detection with parallelized voting procedure, local maximum algorithm and FPGA-prototype implementation. Parallelization of the global design is realized on the basis of θ-value discretization in the Hough space. Four major hardware modules are developed for edge detection in the original video frames, computation of the characteristic edge-pixel values (ρ,θ) in Hough-space, voting procedure for each (ρ,θ) pair with parallel local-maximum-based peak voting-point extraction in Hough space to determine the detected straight lines. Implementation of a prototype system for real-time road-lane detection on a low-cost DE1 platform with a Cyclone II FPGA device was verified to be possible. An average detection speed of 135 frames/s for VGA (640x480)-frames was achieved at 50 MHz working frequency.
URL: https://global.ieice.org/en_transactions/information/10.1587/transinf.2018EDP7279/_p
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@ARTICLE{e102-d_6_1171,
author={Jungang GUAN, Fengwei AN, Xiangyu ZHANG, Lei CHEN, Hans Jürgen MATTAUSCH, },
journal={IEICE TRANSACTIONS on Information},
title={Energy-Efficient Hardware Implementation of Road-Lane Detection Based on Hough Transform with Parallelized Voting Procedure and Local Maximum Algorithm},
year={2019},
volume={E102-D},
number={6},
pages={1171-1182},
abstract={Efficient road-lane detection is expected to be achievable by application of the Hough transform (HT) which realizes high-accuracy straight-line extraction from images. The main challenge for HT-hardware implementation in actual applications is the trade-off optimization between accuracy maximization, power-dissipation reduction and real-time requirements. We report a HT-hardware architecture for road-lane detection with parallelized voting procedure, local maximum algorithm and FPGA-prototype implementation. Parallelization of the global design is realized on the basis of θ-value discretization in the Hough space. Four major hardware modules are developed for edge detection in the original video frames, computation of the characteristic edge-pixel values (ρ,θ) in Hough-space, voting procedure for each (ρ,θ) pair with parallel local-maximum-based peak voting-point extraction in Hough space to determine the detected straight lines. Implementation of a prototype system for real-time road-lane detection on a low-cost DE1 platform with a Cyclone II FPGA device was verified to be possible. An average detection speed of 135 frames/s for VGA (640x480)-frames was achieved at 50 MHz working frequency.},
keywords={},
doi={10.1587/transinf.2018EDP7279},
ISSN={1745-1361},
month={June},}
Copy
TY - JOUR
TI - Energy-Efficient Hardware Implementation of Road-Lane Detection Based on Hough Transform with Parallelized Voting Procedure and Local Maximum Algorithm
T2 - IEICE TRANSACTIONS on Information
SP - 1171
EP - 1182
AU - Jungang GUAN
AU - Fengwei AN
AU - Xiangyu ZHANG
AU - Lei CHEN
AU - Hans Jürgen MATTAUSCH
PY - 2019
DO - 10.1587/transinf.2018EDP7279
JO - IEICE TRANSACTIONS on Information
SN - 1745-1361
VL - E102-D
IS - 6
JA - IEICE TRANSACTIONS on Information
Y1 - June 2019
AB - Efficient road-lane detection is expected to be achievable by application of the Hough transform (HT) which realizes high-accuracy straight-line extraction from images. The main challenge for HT-hardware implementation in actual applications is the trade-off optimization between accuracy maximization, power-dissipation reduction and real-time requirements. We report a HT-hardware architecture for road-lane detection with parallelized voting procedure, local maximum algorithm and FPGA-prototype implementation. Parallelization of the global design is realized on the basis of θ-value discretization in the Hough space. Four major hardware modules are developed for edge detection in the original video frames, computation of the characteristic edge-pixel values (ρ,θ) in Hough-space, voting procedure for each (ρ,θ) pair with parallel local-maximum-based peak voting-point extraction in Hough space to determine the detected straight lines. Implementation of a prototype system for real-time road-lane detection on a low-cost DE1 platform with a Cyclone II FPGA device was verified to be possible. An average detection speed of 135 frames/s for VGA (640x480)-frames was achieved at 50 MHz working frequency.
ER -
English
