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[Keyword] wet etching(2hit)

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  • DC and RF Performance of AlN/GaN MOS-HEMTs

    Sanna TAKING  Douglas MACFARLANE  Ali Z. KHOKHAR  Amir M. DABIRAN  Edward WASIGE  

     
    PAPER

      Vol:
    E94-C No:5
      Page(s):
    835-841

    This paper reports the DC and RF characteristics of AlN/GaN MOS-HEMTs passivated with thin Al2O3 formed by thermal oxidation of evaporated aluminium. Extraction of the small-signal equivalent circuit is also described. Device fabrication involved wet etching of evaporated Al from the Ohmic contact regions prior to metal deposition. This approach yielded an average contact resistance of ∼0.76 Ω.mm extracted from transmission line method (TLM) characterisation. Fabricated two-finger AlN/GaN MOS-HEMTs with 0.2 µm gate length and 100 µm gate width showed good gate control of drain currents up to a gate bias of 3 V and achieved a maximum drain current, IDSmax of ∼1460 mA/mm. The peak extrinsic transconductance, Gmax, of the device was ∼303 mS/mm at VDS = 4 V. Current-gain cut-off frequency, fT, and maximum oscillation frequency, fMAX, of 50 GHz and 40 GHz, respectively, were extracted from S-parameter measurements. For longer gate length, LG = 0.5 µm, fT and fMAX were 20 GHz and 30 GHz, respectively. These results demonstrate the potential of AlN/GaN MOS-HEMTs for high power and high frequency applications.

  • A Proposal of TC-MOSFET and Fabrication Process of Twin Si Channels

    Shun-ichiro OHMI  Tetsushi SAKAI  

     
    PAPER-Novel MOSFET Structures

      Vol:
    E90-C No:5
      Page(s):
    994-999

    Twin-Channel (TC)-MOSFET with twin omega-gate (Ω-gate) Si channels and its fabrication process were proposed. The twin Si channels are able to be fabricated by self-aligned process utilizing wet etching of SiN and silicon-on-insulator (SOI) wafers. Three-dimensional (3-D) device simulation was performed to optimize gate structure for TC-MOSFET with 10 nm10 nm (TSiWG) channels with the gate length of 30 nm, and it was found that TC-MOSFET with right-angled Ω-gate in case the Lunder was 3 nm showed excellent device characteristics similar to the gate-all-around (GAA) devices corresponding to the gate structure as Lunder=5 nm. Fabrication process of twin Si channels was also investigated experimentally, and approximately 40 nm40 nm twin Si channels were successfully fabricated on SOI by the proposed fabrication process.