IEICE TRANSACTIONS on Communications
A High-Speed ATM Switch with Input and Cross-Point Buffers
Summary :
This letter describes a new input and cross-point buffering matrix switching architecture for high-speed ATM switching systems. The proposed switch has input queuing buffers at each input port, and small size buffers for output port arbitration at each cross-point. These two types of buffers share loads using a simple and high-speed retry algorithm. Hardware size is only half that of conventional cross-point buffering switches. In addition, the switch achieves high-throughput at a condition that the switching speed matches the input and output port speed. This switch is expected to enable the development of high-speed ATM switching systems with each port supporting speeds in excess of 1Gbit/s.
- Publication
- IEICE TRANSACTIONS on Communications Vol.E76-B No.3 pp.310-314
- Publication Date
- 1993/03/25
- Publicized
- Online ISSN
- DOI
- Type of Manuscript
- LETTER
- Category
- Switching and Communication Processing
Authors
Keyword
Latest Issue
Copyrights notice of machine-translated contents
The copyright of the original papers published on this site belongs to IEICE. Unauthorized use of the original or translated papers is prohibited. See IEICE Provisions on Copyright for details.
Cite this
Copy
Yukihiro DOI, Naoaki YAMANAKA, "A High-Speed ATM Switch with Input and Cross-Point Buffers" in IEICE TRANSACTIONS on Communications,
vol. E76-B, no. 3, pp. 310-314, March 1993, doi: .
Abstract: This letter describes a new input and cross-point buffering matrix switching architecture for high-speed ATM switching systems. The proposed switch has input queuing buffers at each input port, and small size buffers for output port arbitration at each cross-point. These two types of buffers share loads using a simple and high-speed retry algorithm. Hardware size is only half that of conventional cross-point buffering switches. In addition, the switch achieves high-throughput at a condition that the switching speed matches the input and output port speed. This switch is expected to enable the development of high-speed ATM switching systems with each port supporting speeds in excess of 1Gbit/s.
URL: https://global.ieice.org/en_transactions/communications/10.1587/e76-b_3_310/_p
Copy
@ARTICLE{e76-b_3_310,
author={Yukihiro DOI, Naoaki YAMANAKA, },
journal={IEICE TRANSACTIONS on Communications},
title={A High-Speed ATM Switch with Input and Cross-Point Buffers},
year={1993},
volume={E76-B},
number={3},
pages={310-314},
abstract={This letter describes a new input and cross-point buffering matrix switching architecture for high-speed ATM switching systems. The proposed switch has input queuing buffers at each input port, and small size buffers for output port arbitration at each cross-point. These two types of buffers share loads using a simple and high-speed retry algorithm. Hardware size is only half that of conventional cross-point buffering switches. In addition, the switch achieves high-throughput at a condition that the switching speed matches the input and output port speed. This switch is expected to enable the development of high-speed ATM switching systems with each port supporting speeds in excess of 1Gbit/s.},
keywords={},
doi={},
ISSN={},
month={March},}
Copy
TY - JOUR
TI - A High-Speed ATM Switch with Input and Cross-Point Buffers
T2 - IEICE TRANSACTIONS on Communications
SP - 310
EP - 314
AU - Yukihiro DOI
AU - Naoaki YAMANAKA
PY - 1993
DO -
JO - IEICE TRANSACTIONS on Communications
SN -
VL - E76-B
IS - 3
JA - IEICE TRANSACTIONS on Communications
Y1 - March 1993
AB - This letter describes a new input and cross-point buffering matrix switching architecture for high-speed ATM switching systems. The proposed switch has input queuing buffers at each input port, and small size buffers for output port arbitration at each cross-point. These two types of buffers share loads using a simple and high-speed retry algorithm. Hardware size is only half that of conventional cross-point buffering switches. In addition, the switch achieves high-throughput at a condition that the switching speed matches the input and output port speed. This switch is expected to enable the development of high-speed ATM switching systems with each port supporting speeds in excess of 1Gbit/s.
ER -
English
