IEICE TRANSACTIONS on Communications
A VLSI Architecture Design for Dual-Mode QAM and VSB Digital CATV Transceiver
Summary :
In this paper, a transceiver VLSI architecture is proposed for high speed digital CATV modems, which can perform both the QAM and the VSB transmissions. The proposed architecture of all-digital dual-mode QAM/VSB receiver consists of digital AGC, digital demodulator, fractionally spaced blind equalizer and DFE, digital carrier recovery, and symbol timing recovery. Finite word-length simulation results show that the proposed architecture can achieve an SNR 29 dB for both the 64-QAM mode and 8-VSB mode when the 10 bit ADC input signal SNR is 36 dB, and there are
- Publication
- IEICE TRANSACTIONS on Communications Vol.E81-B No.12 pp.2351-2356
- Publication Date
- 1998/12/25
- Publicized
- Online ISSN
- DOI
- Type of Manuscript
- Special Section PAPER (Special Issue on the Latest Development of Telecommunication Research)
- Category
- Wireless Communication Systems
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Muh-Tian SHIUE, Chorng-Kuang WANG, Winston Ingshih WAY, "A VLSI Architecture Design for Dual-Mode QAM and VSB Digital CATV Transceiver" in IEICE TRANSACTIONS on Communications,
vol. E81-B, no. 12, pp. 2351-2356, December 1998, doi: .
Abstract: In this paper, a transceiver VLSI architecture is proposed for high speed digital CATV modems, which can perform both the QAM and the VSB transmissions. The proposed architecture of all-digital dual-mode QAM/VSB receiver consists of digital AGC, digital demodulator, fractionally spaced blind equalizer and DFE, digital carrier recovery, and symbol timing recovery. Finite word-length simulation results show that the proposed architecture can achieve an SNR 29 dB for both the 64-QAM mode and 8-VSB mode when the 10 bit ADC input signal SNR is 36 dB, and there are
URL: https://global.ieice.org/en_transactions/communications/10.1587/e81-b_12_2351/_p
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@ARTICLE{e81-b_12_2351,
author={Muh-Tian SHIUE, Chorng-Kuang WANG, Winston Ingshih WAY, },
journal={IEICE TRANSACTIONS on Communications},
title={A VLSI Architecture Design for Dual-Mode QAM and VSB Digital CATV Transceiver},
year={1998},
volume={E81-B},
number={12},
pages={2351-2356},
abstract={In this paper, a transceiver VLSI architecture is proposed for high speed digital CATV modems, which can perform both the QAM and the VSB transmissions. The proposed architecture of all-digital dual-mode QAM/VSB receiver consists of digital AGC, digital demodulator, fractionally spaced blind equalizer and DFE, digital carrier recovery, and symbol timing recovery. Finite word-length simulation results show that the proposed architecture can achieve an SNR 29 dB for both the 64-QAM mode and 8-VSB mode when the 10 bit ADC input signal SNR is 36 dB, and there are
keywords={},
doi={},
ISSN={},
month={December},}
Copy
TY - JOUR
TI - A VLSI Architecture Design for Dual-Mode QAM and VSB Digital CATV Transceiver
T2 - IEICE TRANSACTIONS on Communications
SP - 2351
EP - 2356
AU - Muh-Tian SHIUE
AU - Chorng-Kuang WANG
AU - Winston Ingshih WAY
PY - 1998
DO -
JO - IEICE TRANSACTIONS on Communications
SN -
VL - E81-B
IS - 12
JA - IEICE TRANSACTIONS on Communications
Y1 - December 1998
AB - In this paper, a transceiver VLSI architecture is proposed for high speed digital CATV modems, which can perform both the QAM and the VSB transmissions. The proposed architecture of all-digital dual-mode QAM/VSB receiver consists of digital AGC, digital demodulator, fractionally spaced blind equalizer and DFE, digital carrier recovery, and symbol timing recovery. Finite word-length simulation results show that the proposed architecture can achieve an SNR 29 dB for both the 64-QAM mode and 8-VSB mode when the 10 bit ADC input signal SNR is 36 dB, and there are
ER -
English
