This paper proposes a modified per-survivor iterative timing recovery scheme, which exploits a new split-preamble strategy in conjunction with a per-survivor processing soft-output Viterbi algorithm (PSP-SOVA). The conventional split-preamble strategy places a preamble at the beginning of a data sector and uses it to run a phase-locked loop during acquisition to find an initial phase/frequency offset. However, the proposed scheme splits the preamble into two parts. The first part is placed at the beginning of the data sector, whereas the second part is divided into small clusters, each of which is then embedded uniformly within the data stream. This split preamble is utilized to adjust the branch metric calculation in PSP-SOVA to ensure that the survivor path occurs in a correct direction. Results indicate that the proposed scheme yields a better performance than a conventional receiver with separate timing recovery and turbo equalization, and the iterative timing recovery scheme proposed in [1],[2], especially when the timing jitter is large. In addition, we also show that the proposed scheme can automatically correct a cycle slip much more efficiently than the others.

At some point in a digital communications receiver, the received analog signal must be sampled. Good performance requires that these samples be taken at the right times. The process of synchronizing the sampler with the received analog waveform is known as timing recovery. Conventional timing recovery techniques perform well only when operating at high signal-to-noise ratio (SNR). Nonetheless, iterative error-control codes allow reliable communication at very low SNR, where conventional techniques fail. This paper provides a detailed review on the timing recovery strategies based on per-survivor processing (PSP) that are capable of working at low SNR. We also investigate their performance in magnetic recording systems because magnetic recording is a primary method of storage for a variety of applications, including desktop, mobile, and server systems. Results indicate that the timing recovery strategies based on PSP perform better than the conventional ones and are thus worth being employed in magnetic recording systems.

We investigate the design of an interpolation filter of a multi-frequency time division multiple access (MF-TDMA) demodulator which is applied to digital video broadcasting-return channel system via satellite (DVB-RCS). We propose two interpolation filters for symbol timing recovery in a digital receiver where the input analog to digital conversion sampling clock is not synchronized to the transmitter symbol clock. The two proposed interpolation filters are designed by the least mean-square-error at the output of the receiver. Simulation results show that a performance improvement is achieved by employing the proposed interpolation filter.

For a baseband pulse amplitude modulation (PAM) signal limited to Nyquist frequency, mathematical derivation of the timing recovery for a fourth-law circuit followed by a band-pass filter is carried out. The results show that the derived timing wave is expressed as a function of the pulse shape entering the timing path and the bandpass filter tuned to the pulse repetition frequency.

In this paper, we describe statistical properties of timing jitter of symbol timing recovery circuit for carrierless amplitude/phase modulation (CAP)-based very high-rate digital subscriber line (VDSL) system. Analytical expressions of the timing jitter for envelope-based timing recovery system, such as squarer-based timing recovery (S-TR) and absolute-value-based timing recovery (A-TR) schemes, are derived in the presence of additive white Gaussian noise (AWGN) or far-end crosstalk (FEXT). In particular, the analytical and simulation results of the timing jitter performance are presented and compared for a 51.84 Mb/s 16-CAP VDSL system. The A-TR system implemented digitally meets the DAVIC's VDSL system requirement, which specifies the maximum peak-to-peak jitter value of 1.5 nsec and the acquisition time of 20 msec.

We present a case of design and implementation of a high-speed burst QPSK (Quaternary Phase Shift Keying) receiver. Since the PSK modulation carries its information through the phase, the baseband digital receiver can recover transmitted symbol from the received phase. The implemented receiver estimates symbol time and frequency offset using sampled data over 32 symbols without transmitted symbol information, and embedded RAM is used for received phase delay over estimation time. The receiver is implemented using about 92,000 gates of Samsung KG75 SOG library which uses 0.65 µm CMOS technology. The fabricated chip test result shows that the receiver operates at 40 MHz clock rate on 5.6 V, which is equivalent to the 40 Mbps data rate.

In this paper we propose a new timing and phase recovery algorithm to mitigate the inter-symbol interference (ISI) effect and to increase the permissible data rate. We use the mean excess delay of the channel as the timing instant for sampling no matter what symbol rates are transmitted and use the phase of the complex baseband impulse response sampled at the corresponding instant as the carrier phase for compensation. The mean excess delay of a channel is independent of the data transmission rates and can be estimated by the conventional timing recovery circuit by transmitting a low rate data sequence with symbol interval longer than the channel delay spread. We have numerically compared the transmission performances without and with applying our proposed algorithm in the timing and phase recovery. We also compare the transmission performance of the decision feedback equalizer (DFE) when the inputs to the DFE are sampled by the conventional method and by our proposed method. We found that the new scheme has a better performance. Compare with the conventional method, the normalized permissible data rate at a BER threshold of 10-5 and an outage probability of less than 2% can be increased by 5 times. While the new scheme is employed together with DFE, the performance can be further improved. Simulation results for both simulated and physical channels have verified the effectiveness of the new scheme.

We propose a new bit timing recovery (BTR) scheme, called perturbed sampling BTR (PSBTR), that can operate near the symbol rate in high-bit-rate wireless systems. A peculiar sample clock, the duty factor of which is not 50%, is used in the PSBTR scheme. We call this type of clock a perturbed sample clock and use it for clock recovery. In PSBTR, there is no cycle slip of the sample clock, and the PSBTR circuit is mostly digital. We examine the performance of the PSBTR scheme under additive white Gaussian noise (AWGN) by computer simulation and experiment, and from these results, clarify the relationship between the performance and circuit parameters of the PSBTR circuit. The overall results indicate that the PSBTR scheme performs well and can be employed as a BTR scheme for high-bit-rate wireless systems.

We present a receiver structure with joint blind equalization, carrier recovery, and timing recovery. The blind equalizer employs a decomposition transversal filtering technique which can reduce the complexity of convolution to about a half. We analyze the performance surface of the equalizer cost function and show that the global minima correspond to perfect equalization. We also derive proper initial tap settings of the equalizer for convergence to the global minima. We describe the timing recovery and the carrier recovery methods employed. And we describe a startup sequence to bring the receiver into full operation. The adaptation algorithms for equalization, carrier recovery, and timing recovery are relatively independent, resulting in good operational stability of the overall receiver. Some simulation results for cable-modem type of transmission are presented.

In this paper, a transceiver VLSI architecture is proposed for high speed digital CATV modems, which can perform both the QAM and the VSB transmissions. The proposed architecture of all-digital dual-mode QAM/VSB receiver consists of digital AGC, digital demodulator, fractionally spaced blind equalizer and DFE, digital carrier recovery, and symbol timing recovery. Finite word-length simulation results show that the proposed architecture can achieve an SNR 29 dB for both the 64-QAM mode and 8-VSB mode when the 10 bit ADC input signal SNR is 36 dB, and there are 6 kHz of carrier frequency offset, 110 ppm of symbol rate offset, and -82 dBc carrier phase-jitter at 10 kHz away from the nominal carrier frequency.

This paper proposes a differentially-coded-quadrature-phase-shift-keying (DQPSK) coherent demodulator using a new simultaneous carrier and bit-timing recovery scheme (SCBR). The new DQPSK SCBR (DSCBR) scheme works with a frequently used preamble, whose baseband signal alternates between two diagonal decision points, for example, a repeated bit-series of "1001." With the DSCBR scheme, the proposed demodulator achieves a significantly agile carrier and bit-timing recovery using an open-loop approach with a one-part preamble. To illustrate this, a preamble of 8 symbols is applicable with the Eb/No degradation from the theory over AWGN of 0.2 dB. It is also shown that the proposed demodulator achieves an improvement in the required Eb/No of more than 2 dB over differential detection over Ricean fading communication channels. The channels are modeled for wireless broadband communication systems with directional antennas or line of sight (LOS) paths. This paper concludes that the proposed demodulator is a strong candidate for receivers in wireles broadband communication systems.

This paper presents a new offset-quadrature-phase-shift-keying (OQPSK) coherent demodulation scheme for wireless asynchronous transfer mode (WATM) systems that premise the Ricean fading communication channels (e.g., typically with derectional antennas). The presented demodulator is basically advanced from a simultaneous carrier and bit-timing recovery (SCBR) scheme by newly employing a phase compensated filter and a reverse-modulation scheme for OQPSK. This advancement aims to enhance the carrier phase tracking performance against the phase fluctuation due to the fading and/or the phase rotation caused by the carrier frequency error of the oscillator. Design consideration and performance evaluation of the demodulator are extensively carried out under Ricean fading channels typical of the WATM systems as well as additive white Gaussian noise (AWGN) channels. The evaluation ressults show that the advanced SCBR (ASCBR) scheme achieves a bit-error-rate/cell-error-rate (BER/CER) performance close to ideal coherent detection with a considerably short preamble, e.g., 8 symbols. Specifically, compared with differential detection (evaluated for QPSK with the hard-wired clock), the new coherent demodulator achieves a significant required Eb/No improvement, which becomes larger as the fading condition degrades. This paper concludes that the ASCBR scheme is a strong candidate for the Ricean-fading-premise WATM systems.

We propose a new bit timing recovery (BTR) scheme, what we call Step Sampled BTR (SSBTR), that can lower the sampling clock frequency and shorten the clock phase convergence time, for burst signals in high bit rate wireless access systems. The SSBTR scheme has the following characteristics. A sine wave resulting from the BTR code passing through a Nyquist Transmission System is always used, the sampling clock has a lower frequency than the system clock, and the clock phase of Intermediate Frequency (IF) signal input can be estimated from as few as 3 sampled data. The SSBTR scheme corrects the clock phase only once in a burst signal. Therefore, in some wireless access systems, some kind of operation must be performed after the SSBTR, in order to deal with long burst signals, instability of the system clock, and so on. In other wireless access systems that do not have these problems, clock phase can be fixed by the SSBTR scheme alone. The preformance of the SSBTR scheme with respect to additive white Gaussian noise (AWGN) was examined by computer simulation. In addition, when SSBTR is implemented in hardware, there are imperfections in the circuitry that lead to phase estimation error and thus deterioration, so we studied the effects of several such imperfections by computer simulation. The results of these simulations clarify the performance of the SSBTR scheme.

This paper proposes a new simultaneous carrier and bit-timing recovery (CBR) scheme for offset quadrature phase shift keying (O-QPSK) for agile acquisition over satellite communication channels. The proposed simultaneous CBR scheme employs a preamble shared for the carrier and bit-timing recover, which has a specific bit-pattern designed so that its baseband signal alternates between two adjacent decision points at the symbol rate. Using the preamble, the proposed simultaneous CBR scheme estimates the carrier phase and the bit-timing, simultaneously and independently, by open-loop approach. For comparison, this paper also describes the performance and configuration of a joint carrier and bit-timing recovery scheme, which is expanded for O-QPSK from the one conventionally proposed for QPSK. This paper demonstrates with simulation results that the proposed simultaneous CBR scheme significantly improves the agility of acquisition: a mere 30-symbol preamble is sufficient for low-Eb/No channels typical of satellite communication systems. The proposed CBR scheme is also advantageous from the viewpoint of digital implementation: it processes at 2 samples/symbol and eliminates an analog voltage control clock (VCC). The proposed simultaneous CBR scheme is a strong candidate for TDMA systems that require the high data-transmission and frequency utilization efficiency.

This paper proposes a fast timing recovery method with a decision feedback equalizer for baudrate sampling. The proposed method features two special techniques. The first one is for coarse estimation of the sampling phase. Internal signals of the oversampled analog-to-digital converter at different phases are directly taken out for parallel evaluation. The second technique provides fine tuning with a phase-modification stepsize which is adaptively controlled by the residual intersymbol interference. Simulation results by a full-duplex digital transmission system with a multilevel line code show superiority of the proposed method. The coarse timing estimation and the fine tuning reduce 75% and 40% of the time required by the conventional method,respectively. The overall saving in timing recovery is almost 60% over the conventional method. The proposed method could easily be extended to other applications with a decision feedback equalizer.

This paper presents a fully digital high speed (60 Mb/s) Quadrature Phase Shift Keying (QPSK)/Offset QPSK (OQPSK) burst demodulator for radio applications, which has been implemented on a 0.5 µm Complementary Metal Oxide Semiconductor (CMOS) master slice Very Large Scale Integrated circuit (VLSI). The developed demodulator VLSI eliminates analog devices such as mixers, phase-shifters and Voltage Controlled Oscillator (VCO) for bit-timing recovery, which are used by conventional high-speed burst demodulators. In addition to the fully digital implementation, the VLSI achieves fast carrier and bit-timing acquisition in burst modes by employing a reverse-modulation carrier recovery scheme with a wave-forming filter for OQPSK operation, and a bit-timing recovery scheme with bit-timing estimation and interpolation using a pulse-shaping filter. Results of performance evaluation assuming application in Time Division Multiple Access (TDMA) systems show that the developed VLSI achieves excellent bit-error-rate and carrier-slipping-rate performance at high speed (60 Mb/s) with short preamble words (less than 100 symbols) in low Eb/No environments.