IEICE TRANSACTIONS on Communications
Design and Evaluation of Scalable Shared-Memory ATM Switches
Summary :
This paper proposes a number of simple, yet very effective, cell switching architectures that employ shared memory as a basic switching component. Employing small shared-memory switching has several major advantages. First, by taking advantage of commercially available memory technologies, ATM switch design can be simplified to determining a suitable shared-memory module size, and identifying a proper interconnection among the modules. In this way, switch architectures can be reusable and able to evolve as memory technology advances. Second, shared memory greatly enhances buffer space utilization, allows the implementation of flexible and fair buffer allocation policies for multiple services. The switch architectures presented in this paper offer a number of alternative shared buffering schemes including, shared output, input with shared output, and multistage shared buffering. The proposed architectures employ simple, self-routing, interconnection fabrics. We present several simulation results that demonstrate the superior performance of our switch architectures under uniform, bursty, and non-uniform (or hot-spot) input traffic.
- Publication
- IEICE TRANSACTIONS on Communications Vol.E81-B No.2 pp.224-236
- Publication Date
- 1998/02/25
- Publicized
- Online ISSN
- DOI
- Type of Manuscript
- Special Section PAPER (Special Issue on ATM Switching Systems for future B-ISDN)
- Category
- ATM switching architecture
Authors
Keyword
Latest Issue
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Mohammad ALIMUDDIN, Hussein M. ALNUWEIRI, "Design and Evaluation of Scalable Shared-Memory ATM Switches" in IEICE TRANSACTIONS on Communications,
vol. E81-B, no. 2, pp. 224-236, February 1998, doi: .
Abstract: This paper proposes a number of simple, yet very effective, cell switching architectures that employ shared memory as a basic switching component. Employing small shared-memory switching has several major advantages. First, by taking advantage of commercially available memory technologies, ATM switch design can be simplified to determining a suitable shared-memory module size, and identifying a proper interconnection among the modules. In this way, switch architectures can be reusable and able to evolve as memory technology advances. Second, shared memory greatly enhances buffer space utilization, allows the implementation of flexible and fair buffer allocation policies for multiple services. The switch architectures presented in this paper offer a number of alternative shared buffering schemes including, shared output, input with shared output, and multistage shared buffering. The proposed architectures employ simple, self-routing, interconnection fabrics. We present several simulation results that demonstrate the superior performance of our switch architectures under uniform, bursty, and non-uniform (or hot-spot) input traffic.
URL: https://global.ieice.org/en_transactions/communications/10.1587/e81-b_2_224/_p
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@ARTICLE{e81-b_2_224,
author={Mohammad ALIMUDDIN, Hussein M. ALNUWEIRI, },
journal={IEICE TRANSACTIONS on Communications},
title={Design and Evaluation of Scalable Shared-Memory ATM Switches},
year={1998},
volume={E81-B},
number={2},
pages={224-236},
abstract={This paper proposes a number of simple, yet very effective, cell switching architectures that employ shared memory as a basic switching component. Employing small shared-memory switching has several major advantages. First, by taking advantage of commercially available memory technologies, ATM switch design can be simplified to determining a suitable shared-memory module size, and identifying a proper interconnection among the modules. In this way, switch architectures can be reusable and able to evolve as memory technology advances. Second, shared memory greatly enhances buffer space utilization, allows the implementation of flexible and fair buffer allocation policies for multiple services. The switch architectures presented in this paper offer a number of alternative shared buffering schemes including, shared output, input with shared output, and multistage shared buffering. The proposed architectures employ simple, self-routing, interconnection fabrics. We present several simulation results that demonstrate the superior performance of our switch architectures under uniform, bursty, and non-uniform (or hot-spot) input traffic.},
keywords={},
doi={},
ISSN={},
month={February},}
Copy
TY - JOUR
TI - Design and Evaluation of Scalable Shared-Memory ATM Switches
T2 - IEICE TRANSACTIONS on Communications
SP - 224
EP - 236
AU - Mohammad ALIMUDDIN
AU - Hussein M. ALNUWEIRI
PY - 1998
DO -
JO - IEICE TRANSACTIONS on Communications
SN -
VL - E81-B
IS - 2
JA - IEICE TRANSACTIONS on Communications
Y1 - February 1998
AB - This paper proposes a number of simple, yet very effective, cell switching architectures that employ shared memory as a basic switching component. Employing small shared-memory switching has several major advantages. First, by taking advantage of commercially available memory technologies, ATM switch design can be simplified to determining a suitable shared-memory module size, and identifying a proper interconnection among the modules. In this way, switch architectures can be reusable and able to evolve as memory technology advances. Second, shared memory greatly enhances buffer space utilization, allows the implementation of flexible and fair buffer allocation policies for multiple services. The switch architectures presented in this paper offer a number of alternative shared buffering schemes including, shared output, input with shared output, and multistage shared buffering. The proposed architectures employ simple, self-routing, interconnection fabrics. We present several simulation results that demonstrate the superior performance of our switch architectures under uniform, bursty, and non-uniform (or hot-spot) input traffic.
ER -
English
