The rapid development of Asynchronous Transfer Mode technology in the last 10-15 years has stimulated renewed interest in the design and analysis of switching systems, leading to new ideas for system designs and new insights into the performance and evaluation of such systems. As ATM moves closer to realizing the vision of ubiquitous broadband ISDN services, the design of switching systems takes on growing importance. This paper seeks to clarify the key architectural issues for ATM switching system design and provides a survey of the current state-of-the-art.

While active researches have been continuously made on the ATM switch architectures and the QoS service guarantees, most of them have been treated independently in the past. In this paper, we first explain the architectural requirement on the ATM switches to implement the mechanism of QoS guarantees in the context of ATM congestion control. Then we discuss how a vital link between two should be built, and remaining problems are pointed out.

To construct the future multimedia network, ATM network technology and services should support cost-effective, high-speed interconnectivity and a variety of service-providing functions. Furthermore, as the infrastructure of future multimedia service, the ATM architecture should be adaptable to changes without needing replacement of its core functions and platform capabilities. This paper presents an overview of the current state of development, standardization and deployment of the ATM network service technologies and architecture concept. It also discusses the trend toward the integration of ATM technology and Internet technology. Also reported is the state of development and standardization for the individual ATM technologies and related issues, including access networks, bearer services, signalling, network middleware, and future ATM switching system technology.

This paper presents a new architecture of a high-speed ATM switch. The switch, called FSM (Factorial Style Memory) switch, uses Dual-Port memories to construct a factorial style memory for eliminating the bus contention problem. In order to fit the various applications, based on the proposed switch architecture, several kinds of models are also proposed to construct the larger size of switches. With the same required throughput and cell loss probability, the performance analysis of the switch shows that the number of buffers and average cell delay can be significantly reduced in the proposed switch while comparing to the ATM switches with central shared memory. For satisfying applications that require larger switches, three types of expansion methods which contain size expansion, memory expansion, and size-memory combined expansion are discussed.

Input and output queueing nonblocking switch with feed-back loop is proposed in order to reduce the system delay. It has b head of the line (HOL)'s and b output ports feed-backed into the HOL's of feed-back loop. The cell which receives backpressure over threshold is switched and enters one of these HOL's through a feed-back loop. It provides the cell, which should wait behind the HOL of input queue until the cell in that HOL is served, with opportunity to be served immediately by vacating the HOL of the input queue. We obtain the mean system delay and consider the effect of the size of b by computer simulation. As the results, it is shown that proposed switch with appropriate size of b can reduce the system delay compared to the conventional switch.

In this paper, we propose a high performance highly modular ATM switch architecture known as Bodhi which is suitable for small, large, and very large size ATM switch implementations. Its basic configuration consists of two stages: an input stage and an output stage. The input stage consists of input group modules (IGMs) and output stage output group modules (OGMs). Each IGM-OGM pair is connected by multiple paths which carry cells from IGMs to OGMs. Excess cells at the IGMs are recycled to minimize the cell loss probability. Another module called recirculation module is used to couple several IGMs together to create additional routes for recirculating cells which gives this architecture robustness against nonuniform and directed traffic. Multicasting has been implemented by integrating copying and broadcasting techniques, and using some novel techniques to minimize the switch complexity. A shared buffer architecture is employed for OGMs such that it implements multiple priorities dynamically in a weighted manner, requires no speedup, and, can function in standalone mode as small switches. The performance of Bodhi has been evaluated by computer simulation to select design parameters for a 1k 1k (k=1024) switch fabric. It allows growability from 2. 4 gigabit to 150 gigabit switch, and, expandability to 100⁺ Terabit switch with the complexity increasing approximately linearly with size. Based on the study presented in this paper, it is seen that the Bodhi architecture offers a high degree of modularity, weighted dynamic priority control, robustness against nonuniform traffic conditions, low complexity, low latency, and, supports multicasting efficiently and without any limitation. Bodhi, therefore, has high potential for application in high speed broadband networks.

Input and output queueing two stage ATM switch model which is effective under variable hot-spot traffic is proposed. In order to prevent the degradation of performance due to hot-spot traffic, the hot-spot route is added in which cells destined to the hot-spot port bypass. The switch applies the backpressure mode basically. When the switch judges that the hot-spot port exists, it routes cells destined there to the hot-spot route and applies the queue loss mode on them. We evaluate both the cell loss probability and the mean system delay under the nonuniform traffic with variable hot-spot port by computer simulation. As the results, it is shown that our proposed switch can achieve better switching performance than those of conventional switches under variable traffic condition.

This paper discusses an ATM based access system for a broadband access network that provides flexible and cost effective multimedia services for mass consumption including households. The access system proposed herein uses ATM-PDS subscriber transmission technologies, thus enabling multiple users to share a single fiber resource while transmitting or receiving multimedia information within the broadband network. The system also has virtual channel concentration function by using the bearer connection control protocol being studied for V_B5. 2 interface in the ITU-T. We show that the virtual channel concentration function reduces the access cost per user. We also discuss multiple QoS control methods in the system to provide multiple services efficiently. This paper evaluates two methods to handle ABR class and UBR class traffic: shared bandwidth with preferred ABR method, and guaranteed bandwidth with overriding method. The result indicates that when using the shared bandwidth with preferred ABR method for the access system, ABR throughput and UBR throughput per VC depend on the proportion of the number of ABR-VC connections to the total active VCs and on the each buffer size in the access system. And it is difficult to control ABR-VC and UBR-VC throughputs in the access network by using the shared bandwidth with preferred ABR method, which simple mechanism. With the guaranteed bandwidth with overriding method, while ABR-VC throughput and UBR-VC throughput also depend on the proportion of ABR-VCs to the total VCs and on the buffer size, it can offer the minimum guaranteed throughput to the UBR traffic. The result shows the method is effective for easy service provisioning.

The Internet is expected to see a rapid growth in multimedia services in the next few years. Network traffic will increase dramatically for many different services, so it will be necessary to have high-speed broadband backbone networks capable of supporting wide-area coverage. Such networks are expected to be built on ATM technology. This paper describes the next-generation ATM switching node architecture for multimedia communications, the enhancement of system capability and functions, and improved system maintainability. The goal is an ATM switching system for Multimedia Communications switching systems; we call it a Multimedia Handling Node for ATM (MHN-A). MHN-A is based on the concept of a unified architecture for circuit switching, packet switching, and ATM switching. Various functions are provided as options that can be economically added or deleted according to customers' requirements.

This paper proposes a high-speed input and output buffering ATM switch, named Tandem-Crosspoint (TDXP) switch. The TDXP switch consists of multiple crossbar switch planes. These switch planes are connected in tandem at every crosspoint. Even if a cell can not be transmitted to an output port on the first plane, it has a chance to be transmitted on the next plane. Cell transmission is executed on each switch plane in a pipeline manner. Therefore, more than one cell can be transmitted to the same output port within one cell time slot, although the internal line speed of each switch is equal to the input /output line speed. The TDXP switch architecture has several advantages in implementation. First, the TDXP switch does not increase the internal line speed in eliminating Head-Of-Line (HOL) blocking. Second, since the TDXP switch employs a simple cell reading algorithm at the input buffer in order to retain the cell sequence, the TDXP switch does not require to rebuild the cell sequences at output buffers using time stamps, as is required by a parallel switch. These merits make implementing the high-speed ATM switch easy. Numerical results show that the TDXP switch can eliminate the HOL blocking effectively and achieve high throughput both for unicasting and multicasting traffic. This switch architecture is expected to enable the development of high-speed ATM switching systems that can realize over 1 Tb/s throughput in a cost-effective way.

This paper proposes a number of simple, yet very effective, cell switching architectures that employ shared memory as a basic switching component. Employing small shared-memory switching has several major advantages. First, by taking advantage of commercially available memory technologies, ATM switch design can be simplified to determining a suitable shared-memory module size, and identifying a proper interconnection among the modules. In this way, switch architectures can be reusable and able to evolve as memory technology advances. Second, shared memory greatly enhances buffer space utilization, allows the implementation of flexible and fair buffer allocation policies for multiple services. The switch architectures presented in this paper offer a number of alternative shared buffering schemes including, shared output, input with shared output, and multistage shared buffering. The proposed architectures employ simple, self-routing, interconnection fabrics. We present several simulation results that demonstrate the superior performance of our switch architectures under uniform, bursty, and non-uniform (or hot-spot) input traffic.

This paper proposes implementation methods of fast ATM layer protection switching function. The main problem in attaining fast ATM protection is the number of connections in one transmission path. The transmission delay of the signal for protection negotiation procedure is relatively less than the processing time in the end nodes. Therefore shortening of the processing time in the nodes is a crucial factor for fast rerouting. This paper focuses on this point and presents some suitable implementations on ATM nodes for fast protection switching. These architectures can attain protection time of less than 50 ms after the detection of a failure at an end node. The key is load-sharing of the hardware and firmware. This paper also sums up the effectiveness of ATM protection and the current situation of standardization in ITU-T SG13.

This paper introduces and studies the performance of an NN space-division, single-stage ATM switch with dual input-queueing. Each input port has two separate FIFO queues, an "odd" and an "even" queue. An incoming cell is stored at the input at either of two FIFOs according its output port destination (output ports are also labeled as "odd" or "even"). Hence we call this scheme the Odd-Even switch. We compare the Odd-Even switch to the ordinary input-buffered switch and we find that it can achieve a remarkably higher performance, in terms of throughput, mean delay and cell loss. This is due to the fact that the Head-of-Line effect becomes less problematic under the Odd-Even switch. Our results are based on various traffic models. Finally, we compare the Odd-Even scheme to the Look-ahead (input "window") policy.

The Asynchronous Transfer Mode (ATM) and the switches and other network elements based on this principle have matured significantly over the past few years. Extensive field trials have been successfully performed all over the world and an increasing number of operators is starting to offer regular services based on ATM infrastructures. The general trend towards deregulation and liberalization resulting in an increasing competition among network providers world wide creates a strong push towards flexible, high-performance, cost effective infrastructures for data, voice, video and multimedia communication. ATM has the potential to provide the universal platform for this future B-ISDN because it combines the features of classical telecommunication networks with features required to cope with the increasing demand for computer based communication. Therefore, ATM allows a consolidation of all existing, dedicated networks for the various services onto a common network platform and at the same time provides a solid and future proof basis for new services and applications. To make this ATM-based multiservice platform a favorable option for large wide area networks, the reliability known from the classical voice networks has to be provided in addition to a virtually unlimited scaleability of the switching systems and of the network as a whole. Whereas the support of permanent connections, i. e. the application of simple VP-crossconnects, was adequate for the first trial networks, on-demand connections controlled by powerful signaling systems have to be provided in the future broadband networks. Moreover, the rather simple resource allocation and traffic management functions used in the first ATM networks have to be extended to be able to guarantee an application specific quality of service while optimizing the use of the available network resources and, thus, to be able to fully exploit the inherent capabilities of the ATM principle. Another crucial point for the success of the ATM multiservice platform is the efficient interworking with existing networks, especially with the narrowband ISDN, the Frame Relay or SMDS based public data networks and with TCP/IP based Internets. This paper describes a new generation ATM switch which fully exploits the capabilities of todays technology to implement the full functionality necessary to cope with these requirements. It introduces the basic architectural concepts, the functionality and some implementation aspects of this large, highly reliable ATM switch which has been specifically designed for application in the core of a future B-ISDN. Special emphasis is put on the concept and realization of the switch fabric which can be scaled from a few Gbit/s into the Tbit/s range.

Multicasting is an important feature for any switching network being intended to support broadband integrated services digital networks (B-ISDN). This paper proposes an improved multicast packet switch based on Lee's nonblocking copy network. The improved design retains the desirable features of Lee's network including its nonblocking property while adopting techniques to overcome the various limitations mentioned in various literature. The proposed network architecture utilizes d-dilated banyan networks to increase the amount of cells that can be replicated within the copy network. Cell splitting is used to optimize the utilization of the network's available bandwidth. Furthermore, the proposed architecture allows for the modular expansion in capacity to accomodate changing traffic patterns. The modular design of the proposed switch likewise offers easy handling and replacement of faulty modules.

A large-scale modular multicast ATM switch based on a three-stage Clos network architecture is proposed and its performance is studied in this paper. The complexity of our proposed switch is NN if the switch size is NN. The first stage of the proposed multicast switch consists of n sorting modules, where n=N. Each sorting module has n inputs and n outputs and is responsible for traffic distribution. The second and third stages consist of modified Knockout switches which are responsible for packet replication and switching. Although it is a multipath network, cell sequence is preserved because only output buffers are used in this architecture. The proposed multicast switch has the following advantages: 1) it is modular and suitable for large scale deployment; 2) no dedicated copy network is required since copying and switching are performed simultaneously; 3) two-stage packet replication is used which gives a maximum fan-out of n²; 4) translation tables are distributed which gives manageable table sizes; 5) high throughput performance for both uniform and nonuniform input traffic; 6) self-routing scheme is used. The performance of the switch under uniform and non-uniform input traffic is studied and numerical examples demonstrate that the cell loss probability is significantly improved when the distribution network is used. In a particular example, it is shown that for the largest cell loss probability in the second stage to be less then 10^-11, the knockout expander, with the use of the distribution network, needs only be larger than 6. On the other hand, without the distribution network, the knockout expander must be larger than 13.

Multicast ATM switches are essential to support various types of services in the Broadband ISDN. In this paper we present an efficient architecture to support multicasting in shared buffer ATM switches. A lookahead technique is employed to resolve the head-of-line blocking problem in the multicast-queue approach, thus improving the throughput of the multicast traffic. The arbitration between multicast and unicast services is investigated to prevent the lookahead technique from increasing the multicast dominance. We show through performance and complexity comparisons that with a small hardware overhead over the multicast-queue approach, our architecture provides a throughput performance comparable to address-duplication or searchable-queue-based approaches.

This paper describes the design and evaluation of a high-performance multicast ATM switch and its feasibility study, including its 40 Gbit/s LSI packaging. The multicast switch is constructed using a serial combination of rerouting networks and employs an adapted Boolean interval-splitting scheme for a generalized self-routing algorithm. Analysis and computer simulation results show that the cell loss probability is easily controlled by increasing the number of switching stages. It is shown that the switch configuration can be transformed into other patterns to be built from banyan-based subnetworks of arbitrary size for LSI packaging. It is also shown that an LSI chip integrating an 88 banyan-based subnetwork using 0. 25-µm CMOS/SIMOX technology can attain a 40-Gbit/s switching capability.

In this paper, we propose a new multicast address scheme based on bit map address (BA) and vertex isolation address (VIA) schemes. The proposed scheme can be utilized by the self-routing switch in a speed manner, while preserving the multicast capability. We analyze the processing delay of the proposed scheme and show the efficiency.

In this paper, we study an architecture of the growable packet switch with multicasting capability, which consists mainly of a newly proposed multicast cell distributing and copying network and a set of small-scale multicast switch modules. Particularly, we consider a specific implementation method for the multicast cell distribution network that facilitates multicasting and permits modular growth without performance degradation. The switch being studied has the following distinctive features : It can be implemented with small-scale multicast switches or trunk modules. The NN switch fabric can be physically partitioned into small switch modules. The distributed control, self-routing and replication capabilities are preserved. An arbitrarily large switch can be constructed out of modest-size packet switches, without sacrificing overall delay/throughput performance. Each output switch module can be operated independently. Multicast capabilities can be provided in the growable packet switch. Also, we analyze the switch's performance, particularly the packet loss probability according to the distributed knockout principle. From the results, we show that a small increase in the overhead of the output switch module is sufficient to maintain a multicast packet loss probability which is equivalent to that obtained in the non-multicast case.

Predicting the performance of high speed wide area ATM networks (WANs) is a difficult task. Evaluating the performance of these systems by means of mathematical models is not yet feasible. As a result, the creation of simulation models is usually the only means of predicting and evaluating the performance of such systems. In this paper, we use measurements to validate simulation models of TCP/IP over high speed ATM wide area networks. Validation of simulations with measurements is not common; however, it is needed so that simulation models can be used with confidence to accurately characterize the performance of ATM WANs. In addition, the appropriate level of complexity of the simulation models needs to be determined. The results show that under appropriate conditions simulation models can accurately predict the performance of complex high speed ATM wide area networks. This work also shows that the user perceived performance is dependent on host processing demands.

Local Area Networks(LANs)are now being used all over the world. The need for cost-effective and high-speed communication services, such as LAN interconnections and large-volume file transfer of all types of data is rapidly increasing. At the same time, Internet services are spreading rapidly, and well soon see the construction of a cost-effective open computer network (OCN). Frame-relay and cell-relay technologies which can achieve higher-speed and higher-performance switching than packet switching, are therefore attracting much attention. Frame-relay technologies are also important because they provide an infrastructure for high-speed data communication as fast as 1. 5 Mbit/sec. Demand for these frame-relay network services have been increasing rapidly. We propose a cost-effective and highly reliable node architecture that we have developed at NTT. Our basic concept for this is based on the all-band switching node architecture which can provide both STM and ATM switches on the same hardware and software platforms, and can accommodate any type of node, such as STM nodes, and ATM nodes for B-ISDN. Our proposed architecture forms highly reliable frame-relay network infrastructure. By using a scale-flexibility building-block architecture, we can construct a small-scale node and a large-scale node cost-effectively. Next, the key technologies of highly reliable node architecture are presented. These are methods of changing over following function-units without frame-loss and/or cell-loss. We present two examples: frame-relay protocol processing units(PPUs)with an N+M-redundant architecture that consists of a number of acting PPUs(ACT)and a number of standby PPUs(SBY)waiting to become active, and duplicate ATM Mux/DemuX blocks(ATM MDXs)with a cell shaping buffer.

We propose a hardware-based packet forwarder for multi-gigabit IP backbone networks. The conventional Internet deploys routers as a key block, but its software-controlled architecture makes it hard to scale up the packet forwarders, especially for table-lookup processes. We propose introducing a pure connectionless (CL) switching approach with a hardware-based forwarder to construct the core part of a scalable IP multi-gigabit backbone. Compared to a software-based forwarder, the table-lookup time is reduced to 100 ns by using content-addressable memory. This hardware-based pipeline implementation easily achieves a maximum forwarding performance of up to 9. 6-Gbps, or 23 million packets per second, for applications ranging from traditional best-effort IP applications to newly emerging time-critical ones. We also consider additional processing when transferring IP packets to enhance best-effort quality. This is done using selective packet-level discarding, including early packet discard and its enhancement, to achieve minimum bandwidth guaranteed service at the packet level. We discuss the IP backbone scalability issue from the viewpoint of new IP-forwarder technologies, paying special attention to connection-oriented (CO) vs. CL switching and hardware vs. software implementation. A pure CL switching solution consisting of a CL server (CLS) and a CL client (CLC) is proposed to balance the hardware- and software-based CL transport functions. As a first step to this solution, a compact CLS has been developed. It supports 600-Mbps throughput and up to 9. 6-Gbps forwarding power using a modular architecture. It was evaluated in an ATM field trial using an experimental network. The results show the effectiveness of our approach to providing enhanced best effort services.

The ATM switching system accommodating the public switched telephone network (PSTN) and narrowband ISDN (N-ISDN) subscribers should ensure the continued support of existing services and applications and guarantee the same quality of voice services for the telephone users. The voice message connection control discussed in this paper is one of the various technical issues for voice services in the interworking function unit, IWF between asynchronous transfer mode (ATM) node and existing synchronous transfer mode (STM) node [2]. We describe the technical points for the implementation of the voice message connection control with the consideration of the development time and cost. And then we discuss several technical problems such as mapping pulse code modulation PCM coded voice data into an ATM cell, different switching operation, keeping performance of the ATM-PSTN interworking system and then present benefits of the voice message connection control processing from the hardware/software point of views.

This paper presents novel multimedia ATM networks which are capable of transmitting voice data efficiently and unify the switching methods among heterogeneous traffic. Fully ATMized multimedia networks are using fellow cell switches. The proposed assembly method can pack plural calls which have different virtual channel connection (VCC) into one cell. Every call in cells is able to be dynamically rearranged by the fellow cell switch to achieve an efficient use of network resources. The switching functions are supported by shared virtual channel identifier (VCI) cells and fellow cells in it. The fellow cell switch for 622 Mbps links is integrated into a single chip. The multimedia ATM networks including voice transmission can be constructed by the fellow cell switches being attached to the standard ATM switches.

ATM technology can integrate not only new multimedia services but also existing services such as plain old telephone services (POTS) and narrow-band ISDN (N-ISDN) services. We developed ATM subscriber line interface circuits (ATM-SLIC), which can accommodate POTS or N-ISDN subscribers, and a trial ATM access switching system using the ATM-SLICs. This paper proposes embedded trunk functions, a message-type signaling transfer method, an economical ATM interface structure, and a cell-based system control method. Moreover, it shows the main characteristics and efficiency of these proposals in terms of experimental data.

This paper evaluates the throughput performance of a switch architecture for broadband networks that is capable of switching variable-length packets. The structure is connectionless, so that no bandwidth reservation takes place before the user packet, or datagram, is transferred. The interconnection network is assumed to be internally non-blocking and provided with input queues. A previous approximated throughput analysis of the proposed system has been carried out under the hypothesis that the length of the offered packets is uniformly distributed. In this work we perform an exact throughput analysis and we show how the actual throughput of the system can be expressed analytically with a simple closed form. Moreover, we consider a more general case of packet length distributed as a truncated exponential. In this way it is possible to account for cases in which short packets are more frequent than long packets or, conversely, long packets are more frequent than short ones. The minimum throughput of the system is obtained when packets are uniformly distributed; a better performance is obtained when short (long) packets are more frequent than long (short) ones.

Asynchronous Transfer Mode (ATM) networks are expected to support a diverse mix of traffic sources requiring different Quality Of Service (QOS) guarantees. This paper initially examines several existing scheduling disciplines which offer delay guarantees in ATM switches. Among them, the Earliest-Due-Date (EDD) discipline has been regarded as one of the most promising scheduling disciplines. The EDD discipline schedules the departure of a cell belonging to a call based on the delay priority assigned for that call during the call set-up. Supporting n delay-based service classes through the use of n respective urgency numbers D₀ to D_n-1 (D₀D₁ D_n-1), EDD allows a class-i cell to precede any class-j (j>i) cell arriving not prior to (D_j-D_i)-slot time. The main goal of the paper is to determine the urgency numbers (D_is), based on an in-depth queueing analysis, in an attempt to offer ninety-nine percentile delay guarantees for higher priority calls under various traffic loads. In the analysis, we derive system-time distributions for both high- and low-priority cells based on a discrete-time, single-server queueing model assuming renewal and non-renewal arrival processes. The validity of the analysis is justified via simulation. With the urgency numbers (D_is) determined, we further propose a feasible efficient VLSI implementation architecture for the EDD scheduling discipline, furnishing the realization of QOS guarantees in ATM switches.

Per-Virtual Connection (VC) queueing allows an ATM switch to schedule cells to be transmitted on a link based on their VC. This alternative to the traditional First-In-First-Out(FIFO)queueing, in which cells from different VCs of the same priority are stored in a common queue, is implemented by some switch manufacturers. This paper assesses the merits of per-VC scheduling in regards to capacity, traffic shaping, and interworking with traffic management mechanisms such as connection admission control (CAC) and use of queue thresholds. The paper also discusses the conditions which favor the use of per-VC scheduling.

Although the performance degradation for TCP/IP over plain ATM during congestion can be reduced if switch buffer management techniques such as Early Packet Discarding (EPD) and Partial Packet Discarding (PPD) schemes are employed. However, we show via simulation that fairness among connections remains a problem. For example, the fairness among packets of different length is a well known unsolved issue for EPD. To improve fairness of TCP and UDP over an Internet backbone, we propose a new technique called the Age Priority Packet Discarding (APPD) scheme to be used along with EPD and PPD. We employ two simulation scenarios to examine the performance of APPD; the MPEG-I video over UDP protocol and the FTP over TCP protocol. The simulation shows that with APPD combined with EPD and PPD, fairness can be well maintained against different packet length, order of connections, as well as different propagation delays. In addition, packet loss probability can be reduced with APPD in all scenarios, and the improvement is especially significant for video over UDP protocol. Finally we discuss the hardware implementation technique of the APPD scheme.

We propose ATM switching nodes with a feedback rate control scheme, AREX, which does not require a large buffer space and does not deteriorate throughput even in large-scale and high-speed ATM-WANs. The goal of our study is to establish the ATM multi-protocol emulation network ALPEN, which is an ATM-WAN architecture for establishing a backbone for multimedia networks. ALPEN achieves an ATM-WAN which is robust against long propagation delays. It also provides high performance without a large buffer space in an ATM-WAN environment. In ALPEN, each transit node informs the edge nodes only its residual bandwidth ratio. The edge nodes support multiple ATM-layer services by emulating them based on the information notified by transit nodes. Our research has been directed towards achieving high performance ABR (Available Bit Rate) service in an ATM-WAN by using ALPEN. The conventional ABR service requires transit nodes to have relatively high calculation power and large buffer space to overcome the effect of the long propagation delays common in WANs. ALPEN node systems have been developed for trials with actual network traffic. ALPEN with AREX reduces the calculation load of transit nodes for ABR service. That is confirmed by the size of the DSP program created for a test system. ALPEN with AREX is, therefore, able to emulate ABR service with higher performance in ATM-WANs, because ALPEN edge nodes are able to indicate the users allowed by ER (Explicit Rate) feedback. The network throughput, maximum queue length at congestion point, and burst transmission rate are determined by simulation. ALPEN with AREX achieves better performances than the conventional ABR network.

Recently there has been an enormous growth in the popularity of the Internet. The provisions of access to the Internet will be one of the principal services of the next generation of access networks. In order to provide cost-effective Internet access over ATM-based broadband access networks, the introduction of an available bit rate (ABR) service class is a promising solution. This paper describes our analysis of ABR behavior over ATM-based access networks focusing on explicit-rate-based rate controls and their round-trip time effects. We also describe the hardware implementation of the ABR-based rate controls.

This paper presents analysis of a congestion control scheme in which a multiplexer notifies upstream traffic sources when its buffer level crosses a preset threshold. Upon notification, the traffic streams are reshaped to a form less likely to cause overflow through rate or burstiness restrictions, or a combination of the two. For the analysis, the traffic is modeled by two Markov Modulated Rate Processes (MMRP's), one for above and one for below the threshold, and an iterative fluid approximation technique is used to determine the buffer occupancy distribution. Simulation results verify the accuracy of the approach, and the analysis is used to study the effect of varying the threshold and shaping function.

Although ATM networks support various traffic requirements, but many data applications are unable to precisely specify traffic parameters such as bit rate. These applications generally require a dynamic share of the available bandwidth among all active connections, they are called available-bit-rate (ABR) service. Due to bursty and unpredictable pattern of an ABR data stream, its traffic control is more challenging than other services. In this paper, we present an improved ABR traffic control approach, called Offset Proportional Rate Control Algorithm (OPRCA). The proposed approach achieves high link utilization, low delay and weighted fair sharing among contenting sources according to the predefined OPR. The implementation is much simpler than that of existing schemes. OPRCA combines an end-to-end rate control with link-by-link feedback control, and employs a buffering scheme that avoids Head-of-Line (HOL) blocking. It can dynamically regulate the transmission rate of source traffic and maintain the real fairness among all active connections. Simulation results have shown the effectiveness of OPRCA in several performance aspects.

We study buffer access policies which provide different loss priorities between two types of services, namely, real-time and nonreal-time services in ATM networks. Real-time services, such as video and voice, require the cell transmission with bounded delay. For these services, their available buffer sizes are limited by the delay bounds. We compare the performance of several buffering policies with bounded delay constraints of real-time services. Numerical results indicate that a simple buffering policy, called limited partial buffer sharing (LPBS) proposed in this paper, has a good performance for efficient use of ATM networks.

We present a collection of new network control protocols for high-speed networks that are geared to overcome some of the important drawbacks of existing protocols, namely (a) the inefficiencies of existing wait-for-reservation type of protocols for multigigabit wide area networks, (b) the implementation difficulties of credit-based flow control schemes, and (c) the packet resequencing problem of deflection-based schemes. Two of the protocols that will be outlined here were designed in the context of the DARPA sponsored Thunder and Lightning project, at the University of California, Santa Barbara, which is a continuing research effort to design and build a virtual-circuit switched, ATM-based, fiber optic network operating at link speeds of up to 40 Gb/s (see, for instance). The third protocol was designed in the context of MOST project, which is a project on (almost) all-optical switching supported by DARPA. All protocols achieve lossless transmission, efficient utilization of the capacity, and minimum pre-transmission delay for delay-sensitive traffic.

A traffic engineering method has been developed to meet the requirements for efficient bandwidth dimensioning and for a practical and consolidated network design method. It characterizes the offered-traffic burstiness on a transit link by using time-series measurement of the aggregate traffic. It estimates future traffic characteristics based on the average traffic volume at that time which is easily derived from trend analysis, i. e. , an x% increase in bandwidth each year and gives the required link capacity. Simulation showed that the parameters estimated using this method fit the actual behavior of a network well. This method enables an appropriate bandwidth to be allocated to a transit link without having to estimate the specific traffic characteristics for each connection over the link. Once the burstiness parameter and its trend have been identified based on this method, it is possible to use a simple traffic measurement method to detect changes in network traffic and feed them back to the engineering procedure.

The paper is focused on the architectural and technological solutions that will allow the transition from small to huge capacity ATM Switching Systems. This path starts from the industrial nodes available today and will arrive at the photonic switching architecture. The progressive introduction of photonics has already started with the use of optical interconnections in ATM nodes of hundreds of Gbit/s. A balanced use of microelectronics and photonics is the correct answer to the Terabit/s switching system challenge. After presenting a modular ATM Switching System, some technological solutions like Multichip Modules and Optical Interconnections are presented in order to explain how node capacity can be expanded. Some results of the research activity on photonic Switching are finally shown in order to exploit the great attitude of this technique to obtain very high throughput nodes.

In the first stage of ATM switching system development, the specifications are sometimes changed in order to match revisions in ITU standards. Fatal problems due to specification changes and unexpected bugs force ASIC redesign and subsequent debugging is seriously restricted. These situations demand the introduction of new hardware design methodologies. This paper proposes a flexible hardware design methodology, based on a novel real-time emulation technique, suitable for large-scale high-speed communication switching systems. The emulation technique offers desirable system performance without Application Specific Integrated Circuit (ASIC) fabrication by using commercial Field Programmable Gate Arrays (FPGAs) along with many simply-structured high-speed interconnect switch devices for multiple FPGA connection. This technique suits line interface units (LUs) that have ASICs operating at about 20 MHz; each LU employs an LU board and emulation boards, both of which have hierarchical structures with sub-boards. The emulation boards are indispensable for realizing prototype systems rapidly and dealing with specification changes. Different types of LUs can be realized by mounting different sub-boards to the common LU board. Each emulation board is attached to the LU board by the same connector used for LU sub-board mounting. Therefore, the proposed structure has the advantage of utilizing a common LU board for system emulation as well as permitting the development of practical systems. To suppress undesirable multiple FPGA partitioning, we propose the emulation board architecture that has two types of sub-boards, each of which carries a different type of FPGA. We produced some portions of the proposed LU and tested the nearly 20 MHz real-time emulation of a complicated ASIC designed to realize ATM cell header conversion functions. The results of multiple FPGA partitioning on the emulation board suggest that the proposed design methodology will yield economic systems that can be freely modified to overcome hardware bugs and comply with future ITU standards.

In this paper, we discuss configurations of photonic ATM (Asynchronous Transfer Mode) switches and their advantages in terms of the number of optical switching devices to be implemented on the system, the number of wavelengths, throughput, broadcast function etc. In particular, we focus on photonic ATM switch architectures which can be built in the near future; that is, with presently available optical and electrical devices. For example, we assume the optical devices such as optical gate switches with 40 dB on/off ratio. In this context, we evaluate 17 types of photonic ATM switches; they are 6 types of input buffer type switches, 6 types of output buffer type switches, 4 types of shared buffer switches, and 1 proposed type. From our evaluation, for cell switching, wavelength division switching technologies are desirable compared with space division switching technologies in the sense that the former enables us to build a photonic ATM switch with the less number of optical gate switches. Furthermore, we propose a switch architecture equipped with optical delay line buffers on outputs and electric buffers on inputs. We show that our switch architecture is superior in the number of required optical gate switch elements under the given conditions.

This paper describes advanced ATM switching system hardware that uses a high-performance and cost-effective MCM-D module as an ATM-layer function device. The MCM-D module is fabricated on a Si-substrate using the stacking RAM technique to reduce module size. The MCM has a 4-layer Si substrate, a high-performance ASIC, 8 high-speed SRAMs, and an FPGA. By using the stacking RAM technique, MCM-D module size is reduced to 50. 8 mm 50. 8 mm. This is 40% of that (100 mm 65 mm) of a double-side mounted sub-board module with conventional packaging (QFP and SOP). The MCM-D module realizes the ATM-layer functions that require a high-performance ASIC with a high-speed (access time 20 ns) and large-capacity (1 MBytes) SRAM cache. The MCM approach is quite effective in increasing memory access speed because it realizes high-density packaging. The MCM-D module is mounted on an ATM line interface circuit, and realizes 150 Mbit/s throughput ATM-layer functions (header conversion and on-line monitoring) in an ATM switching system. In addition, advanced ATM switching system hardware technologies with sub-module structure are also described. The MCM-D module is one of the sub-modules of the system. This MCM technology and sub-module technology can be applied to advanced ATM switching systems.