IEICE TRANSACTIONS on Communications
A High-Performance Multicast Switch and Its Feasibility Study
Summary :
This paper describes the design and evaluation of a high-performance multicast ATM switch and its feasibility study, including its 40 Gbit/s LSI packaging. The multicast switch is constructed using a serial combination of rerouting networks and employs an adapted Boolean interval-splitting scheme for a generalized self-routing algorithm. Analysis and computer simulation results show that the cell loss probability is easily controlled by increasing the number of switching stages. It is shown that the switch configuration can be transformed into other patterns to be built from banyan-based subnetworks of arbitrary size for LSI packaging. It is also shown that an LSI chip integrating an 8
- Publication
- IEICE TRANSACTIONS on Communications Vol.E81-B No.2 pp.284-296
- Publication Date
- 1998/02/25
- Publicized
- Online ISSN
- DOI
- Type of Manuscript
- Special Section PAPER (Special Issue on ATM Switching Systems for future B-ISDN)
- Category
- Multicasting in ATM switch
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Shigeo URUSHIDANI, Shigeki HINO, Yusuke OHTOMO, Sadayuki YASUDA, "A High-Performance Multicast Switch and Its Feasibility Study" in IEICE TRANSACTIONS on Communications,
vol. E81-B, no. 2, pp. 284-296, February 1998, doi: .
Abstract: This paper describes the design and evaluation of a high-performance multicast ATM switch and its feasibility study, including its 40 Gbit/s LSI packaging. The multicast switch is constructed using a serial combination of rerouting networks and employs an adapted Boolean interval-splitting scheme for a generalized self-routing algorithm. Analysis and computer simulation results show that the cell loss probability is easily controlled by increasing the number of switching stages. It is shown that the switch configuration can be transformed into other patterns to be built from banyan-based subnetworks of arbitrary size for LSI packaging. It is also shown that an LSI chip integrating an 8
URL: https://global.ieice.org/en_transactions/communications/10.1587/e81-b_2_284/_p
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@ARTICLE{e81-b_2_284,
author={Shigeo URUSHIDANI, Shigeki HINO, Yusuke OHTOMO, Sadayuki YASUDA, },
journal={IEICE TRANSACTIONS on Communications},
title={A High-Performance Multicast Switch and Its Feasibility Study},
year={1998},
volume={E81-B},
number={2},
pages={284-296},
abstract={This paper describes the design and evaluation of a high-performance multicast ATM switch and its feasibility study, including its 40 Gbit/s LSI packaging. The multicast switch is constructed using a serial combination of rerouting networks and employs an adapted Boolean interval-splitting scheme for a generalized self-routing algorithm. Analysis and computer simulation results show that the cell loss probability is easily controlled by increasing the number of switching stages. It is shown that the switch configuration can be transformed into other patterns to be built from banyan-based subnetworks of arbitrary size for LSI packaging. It is also shown that an LSI chip integrating an 8
keywords={},
doi={},
ISSN={},
month={February},}
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TY - JOUR
TI - A High-Performance Multicast Switch and Its Feasibility Study
T2 - IEICE TRANSACTIONS on Communications
SP - 284
EP - 296
AU - Shigeo URUSHIDANI
AU - Shigeki HINO
AU - Yusuke OHTOMO
AU - Sadayuki YASUDA
PY - 1998
DO -
JO - IEICE TRANSACTIONS on Communications
SN -
VL - E81-B
IS - 2
JA - IEICE TRANSACTIONS on Communications
Y1 - February 1998
AB - This paper describes the design and evaluation of a high-performance multicast ATM switch and its feasibility study, including its 40 Gbit/s LSI packaging. The multicast switch is constructed using a serial combination of rerouting networks and employs an adapted Boolean interval-splitting scheme for a generalized self-routing algorithm. Analysis and computer simulation results show that the cell loss probability is easily controlled by increasing the number of switching stages. It is shown that the switch configuration can be transformed into other patterns to be built from banyan-based subnetworks of arbitrary size for LSI packaging. It is also shown that an LSI chip integrating an 8
ER -
English
